INVESTIGATIONS ON CAPACITOR VOLTAGE BALANCING FOR THREE-PHASE HYBRID MULTILEVEL INVERTER

Abstract

Multilevel inverters (MLIs) are advanced dc to ac power conversion systems that are gaining much prominence in the field of high power applications. Traditional two level voltage source inverters (2L-VSIs) use series connection of power semiconductor devices to meet with the increased voltage and power demands of the industries, which has reached multi-megawatt level. Nowadays, 2L-VSIs are being replaced with MLIs owing to its several advantages such as better quality output voltage and current waveforms, low harmonic distortion, reduced dv/dt, small common-mode voltage, reduced size of filters and high efficiency. In spite of these advantages offered by MLIs, 2L-VSIs are still popular in the fields where a simple structure and less complex control technique is required. Continued research is happening in the field of MLIs to develop novel or hybrid topologies by modifying or combining the existing MLI topologies. The aim is to achieve maximum number of output voltage levels with less device count, reduced control complexity and high efficiency. Over the past few years, many new MLI topologies have been proposed for various applications. These topologies either have single source or multiple source configuration. Topologies with multiple isolated dc sources are more preferred in photovoltaic applications. Whereas, single source topologies are more suited to back-to-back regenerative applications. The research work carried out in this thesis is mainly focused on single source topologies for three-phase induction motor drives. Single source hybrid MLI topologies are composed of standard MLI units; usually having a primary unit with active dc source and secondary units fed by floating capacitors. Balancing of floating capacitors is the main control task, which is normally carried out with help of pole voltage redundancies. In the absence of redundant states, special control techniques like model predictive control, fuzzy logic control etc. needs to be implemented. Maximum dc bus utilisation of a hexagonal space vector structure based VSI is obtained during square wave or six-step operation of the inverter. This corresponds to a fundamental phase peak voltage of 0.637 dc V , where dc V is the dc-link voltage of the inverter. Whereas, linear modulation range of the inverter is limited to a maximum fundamental phase peak voltage of 0.577 dc V . Overmodulation techniques are commonly employed to achieve full dc bus utilization but this results in substantial amount of low order harmonics in the inverter phase voltage. Higher sided polygonal space vector structures are introduced to extend the linear modulation range but that comes with additional complexity. Cascaded hybrid MLI topologies with capacitor fed H-bridge ii (CHB) units are found to have a unique feature to enhance its dc bus utilization by improving the linear modulation range. This requires special techniques to balance its capacitor voltages at higher values of modulation index. The research work is concentrated mainly on cascaded hybrid MLIs having CHB units and their capacitor voltage balancing techniques. The advantages of cascaded hybrid MLIs over the existing MLIs are identified by means of comparative analysis. These topologies require single source for three-phase configuration and fewer number of active devices and capacitors. Due to its voltage boosting capability, it stands ahead of other single source MLI topologies. The capacitor voltage balancing algorithms used for such hybrid MLIs are more or less same and hence, it is explained here with the help of a hybrid MLI composed of three level T-type neutral point clamped (TNPC) inverter and a floating capacitor (FC) fed H-bridge unit per phase. Based on the ratio of FC voltage and the dc-link capacitor voltage, the number of output voltage levels can be varied. For a 1:2 ratio, the inverter can be operated either as a redundant non-boosting five level inverter or a semi-redundant boosting seven level inverter. When operated as a five level inverter, the FC voltages can be balanced for the whole modulation range independent of the load power factor (pf). The dc-link capacitor voltages are balanced using zero-sequence voltage injection method. Calculation of required zero-sequence voltage takes into account the actual time ratio of redundant switching states used for FC voltage balancing. This time ratio termed as dynamic time ratio in the proposed work is estimated using an algorithm. The proposed balancing technique provides improved transient performance over its conventional method. Seven level operation of the TNPC-CHB inverter utilizes two outermost pole voltage levels without any redundant switching states, for generating seven voltage levels. These outermost levels are not used during five level operation of the inverter. Due to the absence of pole voltage redundancies at extreme outer levels, the balancing of FC voltages becomes dependent on load pf; unity pf being the worst case. Thus, the maximum modulation index (m) possible for the inverter using sinusoidal PWM technique is limited and is theoretically determined as 0.8. This calls for special FC voltage balancing schemes that helps to increase the linear modulation range of the inverter. Based on the investigations conducted on common-mode offset addition techniques for balancing, three offset addition techniques are proposed, namely square, static and dynamic offsets, which helps to extend the linear modulation range of inverter up to m = 0.835, 0.84 and 0.85 respectively at unity pf. These proposed techniques helps to enhance the dc bus iii utilization of the inverter near to that of six-step operation of the inverter at unity pf, which can be further increased in the case of inductive loads or induction motor drives. Since this enhancement is achieved in the linear modulation region, low order harmonics are not present in the line voltage, unlike that of overmodulation techniques. When the ratio of FC voltage and dc-link capacitor voltage is made equal to 1:3, nine voltage levels are possible from the aforementioned inverter. But this leads to a non-redundant boosting inverter. Similar as the case with seven level inverter, the voltage balancing of FCs demand special control technique using common-mode offset addition. However, due to the nonredundant pole voltage redundancies, the offset addition is required throughout the whole modulation range of the nine level inverter. Using the proposed common-mode offset addition technique, called as level clamping technique, it is possible to balance the FC voltage up to m = 0.91 at unity pf that gives a fundamental phase peak voltage of 0.607 dc V . The dc-link capacitor voltages are also balanced with the help of common-mode offset addition. Among the two common-mode offset generated; one for FC voltage balancing and the other for dc-link capacitor voltage balancing; the final offset to be added with the sinusoidal reference signals is decided using an offset selection logic. A detailed explanation of the proposed capacitor voltage balancing techniques used for cascaded hybrid MLIs is provided in the thesis, supported by mathematical analysis. All the proposed works are verified by simulation in PLECS software and experimentally validated using a laboratory hardware prototype of hybrid TNPC-CHB inverter.