BANDWIDTH AND BACK-OFF ENHANCEMENT IN DOHERTY POWER AMPLIFIER

Abstract

The ever increasing demand for higher data rates and lower power consumption of wireless transmitter has driven the Radio Frequency (RF) Power Amplifier (PA) design towards a significant challenge. With the advent of 5G wireless communication, the expected data rate is going to exceed beyond Gbps. Therefore, broadband and highly efficient PAs are required to meet the demands of upcoming mobile and wireless communications. Doherty PA can be one good candidate to fulfil these requirements. The thesis aims to enhance the bandwidth and back-off of Doherty PA based on the two-stage architecture that can efficiently handle complex modulated signals complying the modern standards. The thesis starts with a discussion on conventional two-stage Doherty PA architecture. Different techniques have been developed to enhance the bandwidth of this architecture, such as the design of broadband load combiner, broadband input splitter network. By using these components in Doherty PA architecture, one can overcome the two main design constraints of conventional Doherty PA architecture: narrowband back-off response and limited dynamic range operation. In the next chapter, a two-stage broadband Doherty PA is designed using a broadband load modulation technique to support backward efficiency enhancement up to 9 dB dynamic range. A Design space is also investigated in terms of load combiner parameters to find the feasible design parameters for high back-off Doherty PA architecture using symmetric devices. The proposed circuit is fabricated on Rogers substrate and experimental validation with high power packaged GaN devices shows that the proposed architecture is able to support efficient amplification up to 8-9 dB back-off in the frequency range 1.7- 2.025 GHz with 45%-63.6% drain efficiency (DE). When tested with modulated signals, the proposed circuit qualifies spectral mask with a digital Predistortion (DPD) technique. Next, a design scheme is proposed to design a broadband load combiner to support broadband load modulation. The design has started with employing load conditions of continuous Class B/J mode to achieve high-efficiency performance at back-off, as well as at saturation level. The judicious selection of load conditions at the device intrinsic plane resulted in foster load trajectories at device extrinsic plane. The generic load combiner is designed to match these trajectories at different power levels. The hardware prototype developed for this concept shows 45%-53% back-off efficiency at ii 6-7 dB back-off power in the frequency range of 1.25-2.2 GHz with Continuous Wave (CW) signals. The developed prototype also maintains its performance with modulated signals. In the next part, digital characterization techniques are applied to improve performance of Doherty PA architecture. From the analysis of frequency effects on the load combiner of chapter 3, it is observed that the digital compensation in terms of input phase can enhance the performance of Doherty PA in terms of output power and efficiency. However, as the phase compensation directly effects the output power, it boosts the efficiency of Doherty PA, but have limited contribution in bandwidth enhancement. Therefore, to analyze the effect of digital compensation on bandwidth enhancement, another degree of freedom is added to the generic load combiner of chapter 4 with independent control of inputs. It is observed that independent control of inputs can enhance the effective load modulation bandwidth of Doherty PA. By splitting the input signal into two independently controlled signals, the Doherty PA circuit achieves more bandwidth than before. Therefore, this chapter proposed a hybrid digital/analog technique to design a broadband Doherty PA complying the modern communication signal standards.