DESIGN OF FAST AND ENERGY EFFICIENT APPROXIMATE DIVIDER

Abstract

In many emerging applications of digital signal processing, approximate computation of each arithmetic block is required. In those applications, there is not a strict requirement of accuracy, but the power consumption and delays are a matter of concern. Many approximated Arithmetic Circuits for Addition, Subtraction, and multiplication have been proposed. Among all the mathematical operations, the division operation is the most complex operation. It consumes more power, and its operational delay has a huge effecton the performance of the complete system. However, some techniques for approximated arithmetic division have been explored, but most of those applied the popular approximate method for multiplication. Some accurate blocks of inexact divider circuitry can be replaced with approximate cells for achieving energy- efficient and faster divider circuitry. They have replaced the multiplication blocks with their approximated versions. In some other techniques the bit size of divisor and dividend is reduced using truncation methods based on trade of between accuracy and energy. The division requires, Subtraction to be performed sequentially. Hence this approach may not be perfect for division. In this proposed technique, the approximated inverse of the divisor is taken using a unique method. Further, It will be having a reduced set of multiplication and shifting operations.