DESIGN OF AXI BUS PROTOCOL USING AXI INTERCONNECT IN WIRELESS SENSOR NETWORKS

Abstract

Modern day wireless sensor networks have sensor nodes which are based on SoC in which the communication between processor interface module and peripherals should be very important for the performance of the whole system so, there are various protocols for this communication so one of the widely used protocol is AXI Protocol. For every communication happening there will be one master and one slave and if there will be more than one master and one slave, i have to use AXI Interconnect in between them so in this project i will use MicroBlaze as a Softcore IP of a processor which will be act as a master and there are multiple slave which is AXI UART, AXI Timer and AXI Interrupt controller as well as two other memory-mapped slaves which is SDRAM and BRAM Controller through which read and write operation will be performed so that we will made a suitable connection so that transfer happens faster which will result in a high performance of a SoC and other aim of the project is to get a power efficient design also we have to observe some other parameters in the design like timing parameter and schematic of the design.