DESIGN OF 32 BIT RISC V PROCESSOR FOR WIRELESS SENSOR NETWORKS

Abstract

Wide use of IoT lead to sensor node in Wireless Sensor Network handling a lot of sensed data and therby putting pressure in the network core. A processor is necessary to manage this vast volume of data. This project presents a solution to this challenge. And reduced cycle time, greater performance, and time-to-market concerns are all requirements for the processor technology. So this processor is based on RISC Instruction Set Architecture. Reduced Instruction Set Computer (RISC) has brought benefits to embedded platforms providing software support for devices with minimal hardware cost for decades implementation. This Processor was simulated with MODELSIM. Test bench waveform of various part of the processor are introduced and the system architecture is shown. RISC processor core is a high performance 32-bit microprocessor. This Processor is divided into five pipeline stages that will improve its speedup, which are instruction fetches (IFs),Instruction decoding (ID), instruction execution (EX), memory (MEM), and writeback (WB). The Instructions that have been implemented in the designed processor are as follows. R - type instructions such as ADD,SUB,AND,OR,SLT and instructions such as ADDI,LW,SW,BEQ.