INVESTIGATION OF FERROELECTRIC HZO-BASED MFM AND FeFET

Abstract

CMOS compatible ferroelectric HfO2, particularly hafnium zirconium oxide (HZO), has gained a lot of attention due to its applications such as ferroelectric field-effect transistors (FeFETs), ferroelectric random-access memory (FeRAM), ferroelectric tunnel junctions (FTJs), negative capacitance field-effect transistors (NCFETs), synaptic devices, and in-memory computations. The capability of HZO-based materials to generate reliable ferroelectric behavior at a small thickness enabled the much-needed scalability in the FeFETs. Based on the literature review, we investigate the following problems in the HfO2-based ferroelectric devices: (i) endurance behavior of the HZO MFMs at elevated temperatures, (ii) gate length scaling behavior of FeFETs, and (iii) FeFETs with a reduction in the number of domains due to scaling of the ferroelectric layer. Polarization variation with field-cycling (endurance) of the HfO2-based ferroelectric films due to wake-up and fatigue restricts their usage in non-volatile memory (NVM) applications. In this work, we study the field-cycling behavior of ALD deposited ferroelectric HZO with TiN electrodes. We investigate the effect of temperature on endurance, capacitance, and leakage of the MFMs. We observe a lower wake-up than the reported data attributed to the nitrogen-rich TiN electrodes leading to a limited interfacial layer. We also observe an increase in the remnant polarization, Pr with temperature initially, and the reduced rate of Pr degradation in the fatigue phase at elevated temperatures. The increase in the Pr of the devices at elevated temperatures is attributed to the strong de-pinning. The calculated trap barrier energy of 1 eV in the fatigue phase points towards oxygen vacancy generation in the film. The lower activation energy found in the fatigue phase suggests a higher de-pinning rate for the devices. The reduced rate of Pr degradation in fatigue is attributed to two-competing mechanisms: (i) vacancy generation (leading to domain pinning) and (ii) temperature-dependent de-pinning. The results presented provide key insights into degradation mechanisms which are crucial for improving the reliability of HZO films. In conventional MOSFETs, gate-length scaling effects are limited to the silicon channel; however, in FeFETs, there is a need to consider the 2D distribution of polarization and electric field distribution in the gate stack. In this work, we investigate the gate-length scaling of FeFET and its impacts on memory performance and reliability using the calibrated simulation setups in Sentaurus TCAD. Due to gate-length scaling effects in FeFETs, we observe a lateral non uniformity in the polarization of the ferroelectric layer along the channel. With gate-length i scaling, the remnant polarization shows opposite trends, i.e., Pr reduces for program and increases for erase. This gives a nearly constant 2Pr; thus, we find a relatively stable memory window with gate-length scaling. Also, with gate-length scaling, there is a significant rise in the electric field across the interfacial layer (IL) for the erase state, which is a critical concern for reliability. Gate-length scaling has resulted in a larger decrease in Vth and higher sub-threshold slope (SS) for program state due to a reduction in gate-control compared to erase state. Our results provide crucial insights into the design optimization of nanoscale FeFET for high density and low power applications. With the gate-length scaling in FeFETs, the length of the ferroelectric layer is aggressively scaled down to a few or even a single domain. In this work, we investigate the effect of multi domains versus few/single-domain behavior in FeFET. The abrupt polarization switching behavior of a single-domain is obtained by modifying the Preisach model in which the difference between saturation and remnant polarization (Ps−Pr) is reduced. We find that the memory window (MW) is linearly dependent upon the reduced difference between Ps and Pr. In the limiting case of a single domain, nearly a two-times higher memory window compared to a multi domain FeFET can be obtained. Further, at fixed P/E voltage, the scaling behavior shows improved variability due to increased polarization-induced vertical field with single-domain FeFET. We demonstrate an optimized single-domain FeFET at lower P/E voltage ±2.4 V with the same device performance of multi-domain FeFET at ±5 V, which is highly promising for low power applications. Our investigation highlights that an optimized process can be used to reduce wake-up and the competing role of de-pinning and vacancy generation in determining the evolution of endurance behavior. These findings can help design a ferroelectric FET with better reliability and endurance. Our investigation shows that scaling of FeFET leads to variation in Pr and E-field in IL due to increased short channel effects, which can impact the reliability. We show that a single domain FeFET can obtain a higher MW, which has a high potential for low power applications. These findings will serve as valuable guidelines for designing high-performance and reliable FeFETs.