DESIGN AND ANALYSIS OF ENERGY-EFFICIENT SPINTRONICS BASED CIRCUITS

Abstract

Over the past few years, the conventional silicon complementary metal oxide semiconductor (CMOS) technology is facing challenges in scaling down while maintaining its performance. As the physical dimensions of the CMOS device are reaching its limitations, there is an escalating demand of non-charge based emerging non-volatile memory (NVM) devices. Among the various researched NVMs, spintronics device has emerged as a potential candidate due to its numerous advantages, such as negligible leakage current, energy-efficient, high-endurance, scalability, and compatibility with CMOS devices. Magnetic tunnel junction (MTJ) is the basic storage unit that utilizes spin orientation of an electron and its magnetic moments (up-spin and down-spin) as the state variables. Several advancements, in terms of switching techniques and geometrical variations, have been investigated in the past few decades in order to enhance the performance of spintronics devices. Recently, it has been reported that these progressive spintronics based memories are capable of performing computing (or logic) operation within the memory block itself. This idea has given another altitude to the field wherein various spintronics based computing-in-memory (CiM) architectures have been investigated and reported by many research groups. These CiM architectures overcome the data trafficking, processing time, and power hungriness issues between memory and logic (or computing) units of the conventional von Neumann computing. Hence, CiM functionalities are being utilized for the implementation of brain-inspired neuromorphic computing. Moreover, researchers are constantly aiming to latest techniques, in terms of architecture, algorithms, circuits, and devices, for more efficient and reliable neural networks (NNs). Henceforth, spintronics based CiM designs have dwelled in the implementation of the faster, negligible leakage power, and energy-efficient NNs. Furthermore, these spintronics based NNs are well-versed for demonstrating various artificial intelligence (AI) applications including image recognition, video processing, internet-of-things (IoT) systems, random number generators, speech/voice recognition, handwritten digit recognition, and so on. Spintronics is one of the most efficient ways to physically realize the desirable CiM designs due to ease in performing the computing within the memory cell itself. However, the current spintronics based devices are facing critical concerns in terms of high-integration density, more efficient devices, and the complex CiM architectures. These concerns can be dealt with in two ways as presented in this thesis work. Firstly, by developing a compact model of spintronics based device that is capable of enhancing the performance in terms of energy-efficiency, high i integration-density, thermal stability, reduced error rates, and more controllability. Secondly, by designing an efficient, easily realizable, stable, and reduced cost-per-bit CiM architectures that are capable of performing neuromorphic computing. Hence, at first, this thesis work presents device modeling of an energy-efficient multilevel (or multi-bit) voltage-controlled spin-orbit torque memory (MV-SOTM). Afterward, an improved CiM architecture using MV SOTM is reported, the same is then used for the demonstration of an AI application. The two proposed memory devices, series and parallel MVSOTMs, significantly reduce the average write power as compared to the recently reported multilevel spin-orbit torque (SOT) memories by 91.5% and 49.6%, respectively. Furthermore, the device model is used for the implementation of various spintronics based circuits namely, differential spin Hall effect based NVSRAM (DSNVM), CiM architecture based magnetic full adder (MFA), and all-spin binary neural network (BNN) design. The DSNVM circuit provides 40% faster restoration and 16.7% lesser energy, as compared to previously reported spin Hall effect (SHE) based NVSRAM. Furthermore, the CiM architecture for MV-SOTM based MFA shows 29.2% and 12.22% performance improvement, when compared to the recently reported MFA design, in terms of write energy and logic power, respectively. At last, the all-spin BNN design is presented that consists of spin-neuron and spin-synaptic crossbar array. This all-spin BNN design demonstrates a handwritten digit recognition application.