FINFET DEVICE-CIRCUIT INTERACTION IN ANALOG DOMAIN

Abstract

In the last few decades, the planar CMOS technology has headed towards the path of aggressive miniaturization of the device dimensions which led to an excellent improve ment in the chip power, performance, and area. However, the semiconductor industry faced many challenges in terms of short channel effects (SCEs) when the downscaling reached the nanoscale regime. To overcome the scaling limitations, among the various device al ternatives, FinFET emerged as a preferable choice. This is because of its excellent gate controllability, compatible process flow, and suppressed SCEs. The analog performance degrades as the technology scales from a higher technology node to a lower technology node. One of the critical issues is a degradation of the intrinsic gain (gmr0) which is mainly due to the increased impact of the short channel effects with the scaling. FinFET has much higher output resistance and intrinsic gain in comparison to the planar MOSFET resulting in a better analog performance in the sub-20nm regime. FinFET has become one of the mainstream technologies for the sub-22nm low-power, high performance applications and since analog circuits are an inherent part of the integrated circuits. Therefore, it is essential to develop a systematic design technique for a FinFET analog circuit based on its device physics. This thesis strives to bridge the gap of FinFET device-circuit interaction in the analog domain. Firstly, the importance of the extension region on the device operation is high lighted and shown to be critical. This is due to a low doped region in the drain extension arising because of the requirement of an almost intrinsic channel. The existence of a low doped extension region affects all the important device phenomena as the charges in this region strongly modulate with the terminal voltages. Since the understanding of saturation phenomenon in the output characteristics is important in determining an appropriate biasing of analog circuits. Thus, the onset of saturation in a FinFET device has been analyzed and explained using the help of physical parameters such as electron density and drift velocity. Ausable and simply bias-dependent model of drain saturation voltage (VDS,SAT) is proposed to accurately bias the circuit. Moreover, the behavior of analog performance parameters and capacitances in FinFET are analyzed and discussed in that they show different behavior in comparison to the planar MOSFET. By using our VDS,SAT model and the understanding of the behavior of capacitances and small-signal parameters, we investigated the impact of ca pacitive feedback on the FinFET analog circuit. A systematic design approach of a FinFET amplifier with capacitive feedback is presented along with a model to choose the external capacitances to improve the circuit performance. A voltage-controlled oscillator (VCO) is also designed and discussed an approach to improve the tuning range and VCO gain using the feedback capacitances. The low doped extension region has a large potential drop and thus has a high localized heat caused by the self-heating effect. Since this effect is more prominent in the saturation region of the device, thus essential to consider it in analog circuit design. The self-heating i effect (SHE) is a crucial concern in SOI FinFET devices due to its confined structure and nanoscale dimensions. The SHE deteriorates the carrier velocity and threshold voltage, caus ing a severe degradation in the device performance. Since the drive current variation with temperature has always been among critical problems for many analog circuit applications. Thus, it is essential to bias analog circuits in a condition that prevents the circuit operation to change with temperature over a wide range. A possible solution for this issue is to bias the transistor at a temperature-independent gate voltage called the Zero-Temperature Coefficient (ZTC) point where the drain current is temperature independent. However, the non-uniform spread of the lattice temperature and carrier temperature over the device induced by the SHE also affects the device characteristics. Thus, we investigated and discussed that the SHE has a significant impact on the ZTC operating point. We observed that the reduction of the threshold voltage, saturation velocity, and temperature derivative of both the factors due to the SHE are the main cause of the ZTC variation. We also proposed a model to estimate the ZTCbias point for any drain voltage. Furthermore, we discussed the gain stabilization tech nique for FinFET amplifiers. The behavior of continuous increment of the gain with supply voltage is utilized to compensate for the reduction of the gain with temperature variation. In this technique, we discussed that to compensate for the decrease in the gain with a rise in the temperature requires an increment in the supply voltage. A method to determine the com pensation factor is also discussed to achieve stable circuit performance. All the observations in our work are discussed with the holistic approach in the hope that the results would be helpful for any FinFET analog circuit.