ON MODERN APPROACHES TOWARDS THE DESIGN ASPECTS OF THE CENTRAL PROCESSING UNIT

Abstract

The fast growing field of computers lays significant importance on the development of the CPU. This is more so for the design and development of single chip microcomputers. The present work is essentially concerned with the various aspect of the GPU design with respect to its constituents viz., the control unit, data paths and the ALU. To be more specific, Petri nets as a modeling tool, that have the inherent ability in their structure to represent the control and data flow, have been used to model, analyse and design the CPU with particular reference to the control unit and also to explore their utility in the design optimization aspects towards data paths and the control memory of microprogrammed computers. Furthermore, negabinary number system has been utilised for developing alternative hardware circuitry for the ALU. Computer hardware can be thought of at several levels. The register transfer level of description is of importance in the design of the control unit. Such a description lends ah. understanding of tha internal working of the CPU by des cribing actions such as the transfer of information between its functional units and the registers. Petri nets have been Used to model the CPU hierarchically at the register transfer level. The memory elements have been modeled first. For this purpose, the modeling capabilities of Petri nets have been extended, and use of their ability to represent the state of conflict has been exploited. Memory elements being the basic building blocks, have been used subsequently for Petri net modeling of various registers. The Petri net model of these registers has been obtained by representing through Petri net structure the circuitry that implements the associated microoperations. Here also the Petri net extensions have been exploited. The association of time with the firing of the transitions of the Petri net model has been used as a means for determining the execution time of various microinstructions associated with the instruction set. This analysis has been used to establish the clock rate of the synchronous control unit, whereas in the case of asynchronous control unit this aspect has been used for finding the execution time of various instructions of the set, knowing the sequential order in which the microinstructions are executed. Both these factors form the basis of the operating spool of the CPU. Hardwired control for implementing the instruction set has its advantages in terms of faster speed of operation. Sequential machine design approach is one of the approaches for its design. The overall CPU alongwith its control unit can be represented as a finite automata. In this regard, state mini mization of finite automata has an important bearing on its design. The finite automata can be represented by a restricted class of Petri nets. As such, the control unit has been represented by Petri nets, A general algorithm for the state minimization of completely as well as incompletely specified finite automata has been proposed. Petri net interpretation has been given to some aspects of state minimization problem that leads to straight forward solutions and makes the computer implementation simpler as compared to the existing switching theoretic approach for this purpose. In a single chip prooessor, design optimization aspects contributing to saving the processor chip area are of con siderable interest. Data path assignment problem that aims at obtaining a minimal number of buses while still retaining the features of concurrent data transfers as in the dedicated bus organization has been of recent interest. This problem has been tackled starting from a given instruction sot of a dedi cated bus architecture, first by proposing a systematic metho dology for representing the information regarding data transfers and the associated concurrency in the form of a transfer matrix and then obtaining a minimal bus architecture corresponding to the considered dedicated bus architecture. A problem associated in this process is of finding maximum compatible classes of data transfers. It has been given Petri net interpretation and solution obtained, that makes this aspect of the algorithm for finding the minimal bus architecture easy for computerization and lends easy solutions to the problem of finding maximum compatible classes. Another aspect that goes alongwith the data path assign ment for saving the processor chip area is to obtain a control memory with minimal bit dimension. This problem has been linked with that of the minimal bus structure and a comprehen sive procedure for obtaining an optimized microcode for the implementation of instruction set of the dedicated bus structure

considered earlier has been adopted. The two design optimiza tion aspects when taken in unison save considerable chip area for single chip fabrication of the CPU. Towards the design of the ALU, the negabinary base for the number system is of considerable interest, because of the unique representation of both the positive as well as the negative numbers wherein no sign bit is required. Because of this, it is of interest to develop hardware realizations for the basic arithmetic operations. In this regard, a modified approach to handle the twin carries generated in negabinary arithmetic has been suggested. A feature that has invoked attention is to employ the existing binary logic functions for these operations. With this aim in mind, some hardware reali zations in negabinary base employing binary logic functions for these arithmetic operations have been proposed. Finally, the results are summarised and some suggestions alongwith the critical discussions are given for further work.