DESIGN OF NANOSCALE SPIN-TORQUE MEMORY AND LOGIC

Abstract

The modern system-on-chip (SOC) computing architectures embed memory modules with high performance processors aiming the “prompt” manipulation of large amount of information. The pyramidal shape of contemporary memory hierarchy has propelled the quest for a universal memory technology with high storage capacity, least physical footprint, CMOS compatibility, non-volatility, high reliability, and infinite retention time. The spin-transfer torque (STT) and spin-Hall effect (SHE) based magnetoresistive random access memories (MRAMs) have been envisaged to perform the role of universal memory technology fulfilling the next generation computing requirements. The nanoscale perpendicular magnetic anisotropy (PMA) based magnetic tunnel junction (MTJ) devices has incredibly complemented the research efforts that are being made for the advancement of universal memory. The nanoscale spin-torque (ST) MRAMs have paved the way to implement high performance energy efficient logic-in memory (LIM) or computing-in-memory (CIM) architectures. The MTJ devices in existing single level cell (SLC) and multilevel cell (MLC) STT-/SHE-MRAMs are invariably driven by conventional n-channel metal oxide semiconductor (nMOS) access transistor. The planar architecture of nMOS devices consume significant area of these SLC or MLC designs and pose a major bottleneck for the development of high density energy efficient on-chip memory systems. The large footprint coverage of nMOS devices annul the advantages of scalable PMA based MTJ (PMTJ) and the configuration of MLC designs. With better materialistic investigations in the recent past, cylindrical PMTJ devices have been scaled down to equivalent feature size (F) of modern nMOS devices in the range of 10 nm exhibiting low switching current requirements, high reliability, and infinite retention time. Moreover, among the two possible configurations of MLC designs, i.e. series and parallel arrangements of MTJ devices, the series MLC (sMLC) architecture is dwelt much as compared to parallel MLC (pMLC) counterpart. However, till date, the employment of emerging vertical driver technologies instead of planar nMOS for the MLC STT-MRAMs have not been investigated. Moreover, the LIM/CIM designs published so far employ SLC ST-MRAM based array architectures and heavily rely on volatile nMOS logic inputs that restrict the development of high density SOC architectures. Taking cognizance of the aforementioned facts, the work in the thesis defines two fold objectives: First, the design optimization of nanoscale MLC STT-MRAMs for area and energy efficient ultra-fast write and read operations. Second, the usage of novel SLC and MLC differential SHE (DSH)-MRAMs for the implementation of optimized LIM structures. The design optimization of MLC STT-MRAMs is initialized with development of an inclusive MTJ model that is capable of accepting user-defined physical and electrical MTJ parameters. The model is validated with the experimental results of sMLC and pMLC designs. In the next phase, the sMLC and pMLC STT MRAMs have been optimized for area and energy efficient read-write operations. In this work, a high-k dielectric metal gate-all-around (Hk-GAA) silicon nanowire based vertical transistor is employed for achieving an optimistic 4F2 footprint coverage and very high drive current requirements for MLC designs. The read and write error rates have been minimized with higher read and write margins, respectively. In the next phase, a DSH-MRAM is employed for designing primary building blocks of digital designs such as AND/OR/XOR gates and full adder. A DSH-MRAM based novel sMLC structure has been proposed and utilized to construct an area efficient full adder based LIM architecture with minimization of nMOS network. This work provides an insight to the optimization of spin-torque based memory and logic designs with MLC perspectives.