DESIGN OF SUBTHRESHOLD STANDARD CELL LIBRARY AND ITS ON-CHIP CHARACTERIZATION

Abstract

With technology scaling, the Internet of things (IoT) has emerged as a potential and ever-growing technology that creates an eco-system of connected physical objects which are reachable over the Internet. Portable and battery-operated IoT devices are used in industries such as automobiles, specifically self-driving cars, health-care, and ultra-low power applications such as cardiac pace makers, wireless sensors, and many more. As the majority of the low power devices survive with battery power, ultra-low power design techniques, specifically sub-threshold designs, play a vital role in improving the energy efficiency of the portable devices. However, the impact of process variations is dominant in sub-threshold voltage region due to the exponential dependence of drain current on threshold voltage of the device. Additionally, several nano-scale effects such as inverse narrow-width effect and reverse short-channel effect significantly impact the performance of the design operating in the sub-threshold region. Most of the digital SoCs are developed using standard cell design approach to address time to-market. It motivates to design a sub-threshold standard cell library (SCL) operating below the threshold voltage of the transistor, which accounts for the nano-scale effects to achieve optimal energy-efficiency and reduce the overall power consumption of the portable devices. For validat ing the delay values of the timing library of a sub-threshold SCL, it is essential to characterize the delay of the cells at sub-threshold voltage. This thesis focuses on the design of a sub-threshold standard cell library along with its on-chip delay characterization. An ultra-low voltage sub-threshold standard cell library is designed in which the width and length of the transistor are optimized for maximum current to capacitance ratio considering the nano-scale effects such as reverse short-channel effect and inverse narrow-width effect. The pro posed SCL has improved performance, reduced area, less sensitivity to process variation, and reduced energy consumption compared to state-of-the-art libraries. The proposed SCL consisting of 45 cells is used for the physical synthesis of ISCAS’85 benchmark circuits and a floating-point i unit. The measurement results for ring oscillator based design, taped out in 130nm technology node, demonstrate a performance improvement of up to 27%, reduction in delay variability of up to 24%, and energy-savings of 18%, compared to the state-of-the-art libraries. The proposed on-chip gate delay characterizer employs reconfigurable ring oscillator (RRO) structure designed for sub-threshold operation. As the gate delay of a standard cell dominantly depends on its input slew and output load conditions, the RRO has the provision to measure the impact of input slew and output load on the delay of gates of the proposed sub-threshold SCL. A total of ten chips, fabricated in 130 nm CMOSprocesstechnology, are tested and measured across different slew, load, and voltage conditions. The measured results are found to closely match with the simulation results of typical corner. The ability of the proposed digital characterizer to vary slew and load condition during delay measurement makes it one of its own kind, which saves area and is suitable for sub/near-threshold voltage operation. Conventionally, the digital designs are operated at a maximum frequency obtained by con sidering the worst-case conditions to account for the impact of PVTA variations present in the design. This leads to performance degradation and power penalty in the typical/best corner de signs. This thesis also proposes two error resilient sequential circuits such as a flip-flop and a latch for sub/near-threshold region, that can tolerate timing errors and are useful for dynamic voltage and frequency scaling applications. The proposed error detecting latch employs true single-phase clock which significantly reduces the clock power. The static and contention-free structure of the proposed EDL makes the design tolerant to PVTA variations and leakage-induced false er rors. The post-layout simulations in 28 nm CMOS technology node show that the proposed EDL achieves a minimum clock power-savings of 31%, average power-savings of 16%, and leakage power reduction of 23%. The 10K rigorous Monte-Carlo simulations show that the proposed EDLis tolerant to leakage-induced false errors and glitches. Alowpower error-masking flip-flop has been proposed, which consists of a true single-phase f lip-flop, an error detector, and an error correction module. The post-layout simulations in CMOS 28 nm technology node show that the proposed error-masking flip-flop has clock power and average power-savings of 83% and 44% compared to the existing error-masking flip-flop at 0.4 V, which makes it suitable for near-threshold designs. The proposed work helps to build a robust, energy-efficient and low power digital designs operating in sub-threshold region by using the proposed sub-threshold standard cell library and the error resilient structures.