DESIGN CONSIDERATIONS FOR ROBUST LOW VOLTAGE CMOS RING OSCILLATORS

Abstract

At advanced technology nodes, a robust clock-generation for Low-Voltage (LV) applications is a challenging task for circuit designers as the transistors operate near to their thresholdvoltages. On architectural front, Voltage-Controlled Ring Oscillator (VCRO) topologies are unable to pump huge current at the oscillating nodes to generate high oscillation frequency, subsequently, delivering wide tuning range with low power, area, phase-noise/jitter, etc. Also, VCRO specifications are achieved by narrowing safety margins for robust design which significantly affects the yield at low voltages. Furthermore, Process-Voltage-Temperature (PVT) variability is severe in LV regime, making conventional design approaches cumbersome, inaccurate, and inefficient. Delay models can be used to optimize circuit performance by analyzing the dependence of various design parameters on the circuit design. The performance specifications and the variability effects, once modeled, can be used to optimize the RO design accurately and efficiently at an early (pre-layout) stage of the design. However, presently RO performance models at low supply voltages are inherited from nominal voltage models which lack generality to address the issues in sub/near-threshold voltage circuit design. During node voltage transitions, the threshold points (such as VDD/2) used to predict the transistor region of operation do not consider exponential current-voltage relationship in sub/near-threshold regime. Further, the sensitivity and reliability issues due to non-linearities such as large over/undershoots in input-output voltage transitions are major challenges for a designer to check system feasibility in the low-voltage regime. These variation related parameters can be modeled to improve the circuit/process/device performance. For robust LV RO design, a variation aware design methodology can be useful for a designer which addresses both performance and variability while integrating ROs in sub-system designs such as those of PLLs or to generalize RO Injection Locking-Pulling phenomenon for multiplier/divider applications. In the first part of the thesis, the conventional VCRO’s disadvantages are overcome by proposing Low-Voltage MOS-Varactor based VCRO (MV-VCRO) topology. On the architectural front, the proposed Bulk-Driven, and Dynamic-ThresholdMV-VCROs overcome the problem of series-stack, and current-starved transistors to deliver high VCRO performance. In the second part of the work, the performance models for Low-Voltage ROs are developed using the input-output transient behavior of the RO stage. We validate our models using post-layout extracted netlist in an industrial PDK. Physics based Transition-Threshold Points (TTPs) models are derived as per the region of device operation. The TTPs are linearly dependent with VDD, width W, length L, Temp. etc at different process corners. Thereafter, these models are used to develop Ie f f based propagation delay PD models of an inverter stage in the LV regime. These PD models are used to calculate FOSC as per VDD, W, L at different process corners. Finally, using the derived relationship, we proposed variation-aware jitter estimation methodology for random (white noise) and deterministic (supply, substrate) noise considering over/undershoots in LV RO design. The methodology is physics based and the effect of noise is related with the change in the TTPs. To address the PVT variations in LV ROs, a variation-aware design methodology is developed for the proposed MV-VCROs. The proposed methodology accurately and efficiently complete the designers goal by including PVT variation during performance parameters extraction (W, L). For this, we developed CV models for MOS transistor as Varactor used to vary the node capacitance in both Ring and LC-oscillators. We extracted Varactor- Threshold Points (VTPs) that divide the capacitance CGG when the transistor moves from deep-depletion to inversion region. This VTP is technology independent and is in relationship with the control voltage VCTRL. Finally, based on TTPs and VTPs, we developed Ie f f current based models of MV-VCROs. These models are technology independent and are used to address both the design performance specs as well as PVT specs at early stage of the design. Injection locking-pulling phenomenon is explored to use RO for multiplier or divider applications. The final part of this work presents theoretical insights for the injection lockingpulling mechanism for a generalized ring oscillator (RO). In this analysis, we addresses the arbitrarily chosen initial assumptions for RO injection-locking behavior Frequency and Time -Domain approach. Post-layout simulations are performed on parasitic extracted netlist at two technologies (CMOS 65nm-bulk and 28nm-FDSOI PDK). Finally, a design methodology is proposed with an accuracy > 95% for injected current fast-settling behavior. The results obtained in this thesis show that the variation-aware effective current delay models using Transition-Threshold Points and Varactor-Threshold Points are accurate enough to predict RO performance in the presence of transistor level systematic variations. These models can either reduce the design time (when accurate SPICE models are available for a technology) or can be used to analyze RO circuit performance at an initial phase of technology development (when no SPICE models are available). Therefore, these models allow a designer to take decision regarding the transistor sizes for oscillation frequency, tuning range, power, area, and phase noise/jitter. This will also reduce number of design iterations.