ESTIMATION OF RANDOM LOCAL THRESHOLD VOLTAGE VARIABILITY USING ON-CHIP CONFIGURABLE RING OSCILLATORS

Abstract

Technology scaling enables large volume integration, which successfully implements a vari- ety of functionalities on the small chip area. The aggressive scaling of transistor dimensions allow to achieve high performance and energy e ciency in digital integrated circuits. How- ever, rapid progress in technology scaling is accompanied by the increased sensitivity to process parameter variations. The e ect of random local process variation in lower tech- nology nodes not only poses a serious issue in designing a reliable system but can also cause degradation in the functioning and performance of the chip. This thesis work focuses on the indirect measurement and characterization of random local process variations (i.e. threshold voltage variation). We proposed three di erent circuit techniques to estimate the process parameter i.e. threshold voltage of the transistor on-chip. These circuit techniques consists of the digital con gurable ring oscillator (RO) based test structures that are simple to design, and process variation is sensed using the time domain parameters such as period or duty cycle of RO which makes the measurement procedure quite easy to handle. A specialized threshold voltage measurement cell (TVMC) consisting of a device under test (DUT) is employed to create a recon gurable ring oscillator (RRO) which enables to estimate the impact of the threshold voltage of the DUT. The di erence of periods of RRO due to two voltage levels i.e Vdd and (Vdd 􀀀 Vth) at the intermediate node provides information about the impact of threshold voltage (Vth) of the DUT. The rst technique estimates the threshold voltage by measuring the period of RRO, whereas the second circuit technique extracts using the duty cycle of an RRO. The extraction of the threshold voltage is almost equal from both the measurements. Hence, the threshold voltage extraction based on period measurement validates the extraction using a duty cycle measurement technique. The maximum di erence in predicting the threshold voltage from the proposed model and through SPICE simulation is found to be less than 5%. The duty cycle of high-frequency i RRO signal containing threshold voltage information is reduced to low frequency using the sub-sampling technique. We proposed an RRO-based sampling clock unit which eliminates the need for external reference clock and saves silicon area up to 13.5 times compared to phase locked loop (PLL) based implementation. The impact of local load variation is included in the extraction of threshold voltage in the TVMC based RRO test structure and other circuits available in literature. The local load changes from one DUT structure to the other due to within-die variation which accounts for 56% error in characterizing DUT threshold voltage. In the third circuit technique, the local load issue is addressed where the supply sensitive RO is used to extract local random variation of the threshold voltage. The proposed supply sensitive RO is independent of the local load variation of the DUT by employing a very large value of decoupling capacitor of the order of 2 pF which shields the load variation of the DUT. The supply noise due to the oscillation of RO is suppressed using a decoupling capacitor. The proposed detector also improves the process sensitivity as it tracks the changes observed from the power supply of the RO. All the proposed test circuits are completely digital in nature which are suitable for on-chip implementation. A test chip is fabricated in a 130 nm technology node to show the feasibility of estimating the threshold voltage variability from the proposed test structures. The proposed TVMC technique has a major advantage for self-validating the accuracy of the measurement process and also solves the problem of unequal loading by using a dummy structure. The measured data over 300 identical DUTs within a chip indicates weak intra-die spatial correlation in this technology node which con rms the random nature of threshold voltage variation. We have also discussed the application of the process monitor where it shows how the proposed TVMC based process monitor circuit tracks the delay of the critical path of the design so as to meet the timing requirement or to allow the leakage reduction of the design by employing body biasing techniques. This helps the circuit designers to eliminate the large design margin due to global variations. From the simulation, it is observed that the 87% leakage reduction is possible while meeting the 312 MHz operating frequency timing requirement with the proposed replica critical path circuit at 0.8 V supply voltage. The proposed scheme is also useful to compensate for the slow corner variations.