Characterization of Low Frequency Noise in Silicon Nanowire MOSFET and Related Implications

Abstract

Nanowire transistors are electrostatically favorable for MOSFET scaling as per the technology roadmap. Hence, electrical characterization of nanowire MOSFET becomes crucial, especially towards the assessment of its mode of current conduction and also knowing the influence of gate oxide traps to it. However, due to lack of body contact in nanowire, its electrical characterization is challenging and many of the conventional characterization schemes do not serve. Within the scope of the present work, we have instead employed low frequency noise (LFN) as the characterization scheme for both un-stressed and stressed nanowire MOSFETs, so as to answer some of the unsolved problems pertaining to current transport in silicon nanowire MOSFET and impact of gate oxide traps on it. First of all, we found that, conduction mode in stressed narrow diameter nanowire differs from the usual bulk mode of conduction as found in the unstressed MOSFET, and it evolves like a partial surface mode of conduction because of electron tail spreading into the gate oxide. The phenomenon was furthermore validated with correlated normalized noise current power spectral density and normalized transconductance, measured in field stressed nanowire MOSFET, and a deviation was found from the standard Hooge model of the noise. The second part of the work has been dealt with assessing the role of gate oxide traps, which promote a multi-level random telegraph noise (RTN) behavior in the drain current found in wide diameter nanowire MOSFET. Moreover, we have observed a gate voltage overdrive dependent state suppression effect in the multi-level RTN trace, which was explained from a conceptualized two-trap model hypothesized employing a non-uniform but contiguous stress distribution within the gate oxide of the nanowire that resulted because of finite curvature of the silicon nanowire. Detail energy offsets calculated between the two traps successfully show the carrier exchanges via traps and explain the anomalous bias dependency of the RTN, which results to different capture and emission time of carriers than the trend predicted by the conventional Shockley-Read-Hall (SRH) statistics. Clearly, bulk traps though impact the current conduction in nanowire MOSFET, but its concentration can presumably be different at the edge of the nanowire because of imperfections of the gate oxide at the edges. Hence, in the final part of the work, we extracted oxide edge trap density through LFN measurement in a gated diode like arrangement of silicon nanowire, and furthermore derived a closed form noise model. Oxide edge trap density was found different than the oxide bulk trap concentration, and our devised noise measurement scheme complemented by modeling seems suitable to improve the resolution of the oxide edge traps