Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/1880
Title: FPGA BASED CHIP DESIGN FOR DC-DC CONVERTER
Authors: Chander, Subhash
Keywords: ELECTRICAL ENGINEERING
DISTRIBUTED POWER SYSTEM
FPGA BASED CHIP DESIGN
DC-DC CONVERTER
Issue Date: 2011
Abstract: Every electronic system needs a source of constant voltage supply for its operation. The DC-DC converters generally used to obtain desired DC voltages play an important role in powering telecom and computing systems. The buck converter topology is the most widely used topology in variety of applications viz. low voltage-low current in portable consumer electronic gadgets (mobile phone, personal digital assistants etc.), low voltage-moderate current for on-board applications and low voltage-high current applications such as Microprocessor Voltage Regulation Modules (VRM). The Distributed Power System (DPS), a multi-stage approach, is becoming the standard in telecom, mainframes computers, workstations, servers, laptops and desktop computers. This system provides standardized design, ease of customization, maintainability, high packaging, high power density, good reliability, and high efficiency without significant increase in cost. The system requirements are allocated to a number of small power processing units, which are distributed throughout the system, with the intent of bringing power processing as close as possible to the point of use. The computer systems are the prime candidates for the distributed power due to their large usage of low voltage power. Computer system involves large number of devices and ICs, distributed all across the systems, which operate at different voltages. Many computer systems now use 3.3V, 5V, and 12V buses to distribute power on-board for high efficiency point-of-use conversion. This cuts down the size of the electrical distribution wires and allows rapid changes in load requirements to be handled close to the source of the transients. The Intermediate Bus Architecture (IBA) is an emerging distributed architecture in high performance on-board power delivering systems for computing, networking and industrial applications. This architecture includes a DC-DC converter called bus converter which is, powered by a conventional backplane typically 48V. It provides at its output a DC bus, depending on the application, which can be regulated, unregulated or quasi-regulated voltage typically ranging from less than 5V to over 13.8V. In IBA the buck converter steps down the intermediate bus voltage to the pay load levels on the electronic board. The 48V backplane is normally stepped down to a lower intermediate bus voltage of 24V, 12V or 5V to the racks of the boards within the system. However, most of the sub-circuits or ICs on the boards are required to operate at voltages ranging from 1V to 3.3 V, at currents ranging from tens of milliamps to tens of amps. Therefore, DC-DC converters are required to step down from 24V, 12V or 5V voltage rails to the desired voltage with its ability to supply the current required by the sub-circuits or ICs. Non-isolated buck converters which generate supply voltages as required from this intermediate bus are called Point-of-Load (POL) converters. The Intermediate bus feeds a number of POLs that provide the required output voltages depending on the load requirements. In the present work Field Programmable Gate Array (FPGA) based chip design of DC-DC converter is considered with special emphasis on the low voltage applications. The literature provides the POL converter chips which are predominated by the analog solutions, due to their low cost and high speed. But, with the rapid increase in the computational power, speed of digital circuits and reduction in cost, digital controllers can be used in high performance DC-DC converters at reduced cost. Advanced control algorithms possess potential of performance improvement; with reprogrammable and re-configurable capabilities, which enhances its flexibility. Despite potential benefits, it has not received broader acceptance in high frequency, low to medium power DC-DC applications due to cost, performance, availability, and/or ease of use considerations. The available FPGA systems either lacked in performance to match with the standard analog controller ICs or are exceedingly complex for the intended applications. In the last few years, digital control and FPGA have experienced an enormous growth in control applications, due to the in^ease in the processing speed, availability of advanced features and decrease in cost on one hand and on the other hand, availability of well established and automated digital design tools to shorten the design cycle. Development of designs using FPGA requires HDL based design, synthesis, simulation and verification tools to target the FPGA. These designs can be easily integrated with other digital systems or modified to suit even new set of specifications. Generally, there are several approaches to implement digital controllers, but custom hardware FPGA and Application Specific Integrated Circuits (ASIC) are better solutions for switching power converters. Concurrency and superior processing speed makes FPGA suitable for high switching frequencies iv and bandwidth. The FPGAs are more flexible because of the facility to specify their size, speed, and price. Behavioral modeling of the IC system represents the functionality of an IC with macro models using more efficient modeling techniques. In the proposed work, MATLAB/SIMULINK and VHDL, tools have been used to develop behavioral models of the POL converter. This is achieved by first developing behavior models of the sub-systems of the POL converter, followed by development of the complete model of the system for its functional verification in MATLAB/SIMULINK. The FPGA based implementation requires, the VHDL based behavior models for different functional blocks. These models are designed using VHDL and verified using Modelsim simulator. After meeting the functional requirements of different sub systems, all the sub-systems are integrated for FPGA based chip for POL converter. All switching DC-DC converters have closed loop control to maintain the output voltage constant. In the closed loop control schemes, loop stability requires different compensation techniques. Typically, PI or PID controllers are used to provide the compensation for gain and phase shift around the control loop in both analog and digital control systems. In digital systems, additional phase shift arises due to time delays in processing the control data stream. This is in addition to the delay caused by the output filter in the analog control. Behavior of the POL converter with different control schemes, are analyzed using SIMULINK models for the power stage. State-space averaging scheme is used to develop a small signal model of the converter in the present work. In the proposed model ideal components are replaced by non-ideal componjnts which include the parameters like DC Resistance (DCR) of the inductor, ESR of the capacitor, and the ON resistance of the MOSFET switches Rds(on)- The discretization of analog controller or digital redesign approach is used in the design of PID controller. In the continuous domain design of the controllers the samplers and zero order holds in the control loop are ignored. This model is discretized to develop the digital controller. Accurate digital redesign approach requires the sampling frequency sufficiently higher than the system crossover frequency of the system. Since the state-space averaged models are accurate only up to half of the switching frequency, the loop bandwidth or crossover frequency for the stable loop is chosen to be less than 1/3rd of the switching frequency. The gain of the controller is adjusted to obtain sufficient phase margin and the high crossover frequency. The crossover frequency should be as high as possible but below the switching frequency to ensure quick response of the DC-DC converter under transients. The phase margin should be sufficient to ensure the system's stability. A positive phase margin of the system in the range of 45° to 60° is desirable for the stability. Transient response of the converter has been analyzed using, SIMULINK models for the different sub-systems like POL power stage, Analog to Digital Converter (ADC), Digital Pulse Width Modulator (DPWM), variable load and variable source. Using these sub-systems complete POL converter model has been synthesized and the simulation is carried out with voltage mode control. Voltage mode control has slow transient response due to the bandwidth limitations. A scheme is presented for discrete PID controller to improve the transient response under source and load disturbances, giving rise to discrete auto tuned PID controller. The transient response of the POL converter is improved by modifying the PID controller parameters online with small alteration in the structure. An important feature of this auto tuned PID controller is that it preserves traditional control structure, and easily incorporates the computable dynamic factor S. Moreover, the proposed scheme is model free since 3 depends only on the recent process states, normalized error eN, and normalized change in error AeN. Simulation results are obtained to study the performance of the converter with variation in load and source. These simulation results are then compared with discrete PID controller. Simulation results show that the discrete auto tuned PID controller has better dynamic performance as compared to discrete PID. The performance of DC-DC converter is affected by the variation in plant parameters during the operation. The linear controller with large modifications of parameters causes slow transition and insufficient damping. In such cases, the dynamic properties of the controlled system, over a wide operating range, can be improved by the use of the Variable Structure Control (VSC) such as Sliding Mode (SM) control. The switching converters are also inherently variable structured systems. To improve the dynamic performance of the POL converter SM control technique is applied due to the ease of implementation. The simulation is carried out to further investigate the performance of the converter. The results of the converter with SM and PID controllers are then compared. The significant reduction in rise time and settling time is observed in transient conditions. However, SM VI controller suffers from the disadvantage of high losses and Electromagnetic Interference (EMI) due to its variable frequency. Low voltage switching DC-DC converters are emerging as major requirement in many present day electronics applications. These applications require different output voltages for different functional modules. A numbers of conventional solutions are presented in the literature with isolated topologies employing transformer. These solutions suffer from poor regulation and have the serious cross regulation problems which along with EMI effect generate large noise and affect system performance. This causes hindrance to on-chip implementations and on-board applications. Power supplies with non-isolated, multi-output voltages are becoming increasingly popular, particularly in on-board applications. Hence, a Single Input Triple Output (SITO) synchronous converter with good regulation on all output voltages is considered. The SITO converter recommended for on-board application is designed, modeled and its digital control is presented. A PWM-pulse delay (PWM-PD) control method is used to obtain the multi-outputs with ability to regulate the outputs. The simulation model is developed and the simulation results are presented for line, load and cross regulations. The performance of the proposed control scheme is experimentally verified for the designed controller parameters. For this, the VHDL based behavior models are used for the different functional blocks of the controller chip for the POL converter with PID control. This is implemented using Xilinx's FPGA as target device, with 100MHz system clock frequency in the fixed point representation. The advantage of the fixed point representation is that it converts all the floating point operations into integer operations. Thus, the fixed point implementation using FPGA makes effective use of on-chip area and makes the digital controller faster. The key modules of the controller chip are: error generator, multiplier/Look Up Tables (LUTs), duty calculator, duty limiter, DPWM, ADC interfacing circuit etc. The PID controller is designed using combination of constant multipliers-adders, and LUTs-adders based implementations. A counter-comparator based DPWM is designed for 400MHz clock frequency for producing an 11-bit duty ratio command into a single pulse. Another, DPWM architecture with fixed dead time for synchronous operation is also proposed. The two digital controller chip architectures designed are implemented on the FPGA device. A prototype of the POL converter is designed and developed for experimental verification in real time VII application. The power stage is designed with emphasis on the speed, efficiency and size of the converter. Miniaturization of system with small size of the components is done by choosing high switching frequency. The performance of the converter is investigated experimentally for steady state and transient conditions. The simulation and experimental results are seen to be in close conformity. Summarizing the above, a complete simulation model of the POL converter is designed using MATLAB/SIMULINK. Extensive simulation has been carried out to verify the performance of the converter with different control schemes. The transient response of the converter is improved with discrete auto tuned PID controller. The POL converter performance is also investigated with a nonlinear control scheme (SM control) and its simulation results are compared with PID control scheme. A non-isolated converter topology (SITO) with digital control is proposed for obtaining three output voltages from the single source for low voltage on-board applications. The FPGA based design of single chip controllers for POL converter is presented. Different sub-systems are designed using VHDL, which are simulated for their functional verifications. The experimental results obtained with designed chips show that the steady state and transient response are within the limits for satisfactory operation. Accordingly, the digital controller chip for low voltage on-board applications can be a substitute of the analog controller chips both technically and commercially.
URI: http://hdl.handle.net/123456789/1880
Other Identifiers: Ph.D
Appears in Collections:DOCTORAL THESES (Electrical Engg)

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