IMPLEMENTATION OF ADIABATIC LOGIC FOR ULTRA LOW POWER APPLICATIONS

Abstract

Energy consumption has become a matter of concern for the implementation of Complementary Metal Oxide Semiconductor (CMOS) based systems due to the high density of integrated devices. New device concepts and novel circuit approaches have been investigated for low energy consumption. Adiabatic switching is a circuit level approach that has made it possible to realize the ultra low power computing applications without reducing the supply voltage and node capacitances. The term "adiabatic" is a thermodynamic term which indicates the charge transfer without generating heat. In adiabatic CMOS circuits the energy consumption is minimized by slowing down the charge transport between the drain and source terminals of the MOSFET switch and recovering the energy from the circuit. A time varying voltage source ensures the slow charge transport, keeping small potential across the on-resistance encountered by the MOSFET switch. The adiabatic switching technique is a good option to implement the ultra low power applications for which conventional energy is limited and speed is not critical such as bio-medical, robotics, space, deep-sea etc. However, the design of an efficient time varying voltage source/Power Clock Generator (PCG), area overhead and development of an accurate energy estimation technique are found to be the main challenges in the realization of an energy-efficient adiabatic circuit. The work presented in this thesis is primarily focused to provide the solutions to the challenges of adiabatic switching technique. The scaling trends are also drawn to appreciate the role of robust ultra low power adiabatic circuits with the technology scaling. The energy efficiency over conventional CMOS circuit can be achieved by the adiabatic circuits if their design metrics such as operating frequency range, intrinsic capacitances and optimized supply voltage are available. An energy estimation technique for an adiabatic circuit is important to find out the advantageous design metrics. Analytical models for estimation of energy consumption of adiabatic logic gates have been widely reported. The reported models have also been validated with simulation results to estimate the energy consumption of adiabatic NAND/NOR gates for maximum fan-in of six. The analytical model for accurate energy estimation of n-input adiabatic gate has not yet been reported. This thesis deals with the development of an analytical model (mathematical equations) for accurate energy estimation and optimized supply voltage for an n-input adiabatic NAND/NOR gate. The model is proposed by considering the following: the on-resistance of a MOSFET switch varies with a change in ramp of the power clock and to calculate the accurate RC products of the switching networks for an input combination of the adiabatic gate. Further, model equations are also employed to draw the scaling trends, the effects of various device and design parameter variations on energy consumption of an adiabatic gate. Results obtained for the proposed model and reported model are extensively compared with simulation results at 90 nm and 65 nm CMOS technology nodes. In comparison of reported model the proposed model closely validates with simulation results. In this thesis the analytical and design techniques are proposed to meet the solutions to the challenges that restrict the use of adiabatic circuits in ultra low power CMOS circuit design. One of them is the design of an efficient PCG that has been an important aspect of the implementation of an energy-efficient adiabatic circuit. During the adiabatic switching the PCG should deliver and recover the energy efficiently. Hence, a PCG should be less dissipative to achieve the maximum possible energy efficiency from an adiabatic circuit. Numerous types of synchronous and asynchronous resonant PCGs have been reported which show the energy efficiency for adiabatic circuits. A synchronous PCG requires the external control signals to maintain the clock frequency of the power clock for the data dependent variations in the adiabatic circuit. Power and area overhead of the control unit of a synchronous PCG are crucial issues that restrict its use to drive the adiabatic circuits. In this thesis the design of an energy efficient synchronous single phase resonant PCG is proposed by using a control unit based on the sense-amplifier based comparator. The proposed PCG shows the energy efficiency than the reported PCG without compromising the area and robustness. For this purpose a study on various circuit topologies of Sense-Amplifier based Flip-Flops (SAFFs) is carried out along with a proposal of a new slave latch for the SAFF. Further, in order to achieve the energy efficiency the energy recovery sinusoidal signal is applied as a clock to the SAFFs that recover the energy from the gate capacitances of associated transistors. A SAFF with an energy recovery sinusoidal clock is called as the Sense-Amplifier based Energy Recovery Flip-Flop (SAER FF). Thus, this work not only carried out the study of SAFFs for PCG design but also propose a strategy for additional energy gain. The proposed SAER FF gives a relatively less Power Delay Product (PDP), area, short circuit current and leakage power with respect to the reported SAER flip-flops. The single phase adiabatic circuits are preferred due to simple clock network, reduced energy loss in power clock generation and less area overhead. In this thesis, a comparative study among the MOSFET (Metal Oxide Semiconductor Field effect Transistor) diode based Single Phase Adiabatic Logic (SPAL) and the reported latch based single phase adiabatic circuits is extensively carried out for circuit structures, energy and delay at 45 nm, 90 nm and 180 nm CMOS technology nodes.