DYNAMIC PERFORMANCE IMPROVISATION IN CURRENT STEERING DIGITAL TO ANALOG CONVERTER FOR HIGH FREQUENCY APPLICATION

Abstract

Data converters play crucial role in high-speed data communication system. Now increase in demand for higher data rates, transmission5G/6G communication system, software defined radio (SDR) and other communication uses Digital to Analog converter with sampling rate may exceed GS/s.High resolution and high-speed DAC are required most communication application. This thesis analyzes and design of a Current Steering DAC using specialized architecture methodology to improve the dynamic performance such as SFDR, SNR. Using special technique such as Dynamic Element matching and segmented architecture to minimizes the transient induced nonlinearity, current source miss- matches. With small area, low power consumption high speed DAC is designed. The designed current steering DAC is operated with sampling frequency of 1GHz and Nyquist frequency of 500Mhz. DAC will use the thermometer decoding, random rotation based binary selection DEM method to provide SFDR >61db and SNR 59db over entire Nyquist bandwidth and power consumption of 30.23mW. The circuit simulation was performed using an 180nm CMOS process, demonstrating its feasibility for integration into modern semiconductor technologies. In addition to the design and simulation of the DAC, this thesis explores various design challenges, such as higher resolution, high sampling speed, SFDR, SNR and power efficiency optimization. Detailed analyses of the modulator’s performance metrics, including linearity, dynamic range, and power consumption, are provided. Comparative studies with existing DAC architectures highlight theadvantages and potential trade-offs of the proposed design. The findings of this work contribute to the ongoing efforts to improvise dynamic performance for higher resolution and high-speed DAC.