ADANCED LEVEL SHIFTER DESIGN FOR OPTIMAL PERFORMANCE IN LOW-VOLTAGE DIGITAL SYSTEMS

Abstract

The reduction of power consumption in CMOS circuits is crucial for the advancement of low-voltage digital systems. One effective approach is using dual supply voltages, where noncritical paths operate at a lower voltage to minimize power usage without affecting overall circuit performance. This thesis explores the design and optimization of level shifters (LS), which are essential for interfacing circuits operating at different voltage levels in dual VDD systems.A comprehensive literature survey covers various existing LS designs, including the conventional cross-coupled topology, current mirror topology, Wilson current mirror level shifter, and C3MLS level shifter. The drawbacks of these designs, such as contention, static power consumption, and inefficiency in converting very low voltages, are analyzed. To address these issues, a novel level shifter is proposed, combining beneficial features of both CCLS and CMLS. The proposed LS uses feedback mechanisms to eliminate static power consumption efficiently and improves performance by ensuring every node is accessible by either pull-up or pull-down paths. Detailed circuit diagrams and simulations illustrate the operation and benefits of the proposed design. Simulation results demonstrate significant improvements in propagation delay, energy consumption, and static power consumption compared to existing stateof- the-art level shifters. The proposed LS shows robustness across various process corners and temperatures, making it a viable solution for low-voltage digital systems. The proposed level shifter is simulated in cadence virtuoso with CMOS 65nm technology . The Post layout simulation’s of the proposed level shifter shows a propagation delay of 6.83ns ,An average Energy per transition of 10.265 fJ for converting 0.3V to 1.2V. The proposed level shifter demonstrates the lowest energydelay product compared to current state-of-the-art designs, with an average static power consumption of 1.45nW at a VDDL of 0.3 V. The average minimum convertible input level, is 150 mV at a 1-MHz input frequency.