ACCELERATING SECURE HASH ALGORITHM – 3 (SHA-3) USING IN-MEMORY COMPUTATION

Abstract

This work presents an In-memory architecture for implementing the Secure Hash Algorithm - 3, which aims to accelerate the computation of hash digest. The proposed design utilizes a novel 5-input XOR operation, read-compute-store (RCS) scheme, and combining the steps theta-3 (θ3), rho (ρ), and pi (π) steps to compute them in the same cycle. The peripherals, such as the decoder, barrel shifter for rotation operation, and write drivers, are designed to support the normal read-write, 2-input, and 5-input boolean operations. This implementation maps the SHA-3 to a 64x64 8T SRAM array and is designed in a 65nm process technology mode. According to simulation results, the proposed architecture can work with the clock with a frequency of 500 MHz and provide 2388 clock cycles latency to compute the hash of a single message block. This yields a throughput of 192 Mbps. The proposed design can be integrated with a processor to provide instructions or with an in-situ controller to control the sequence of operations without the involvement of the processor.