DESIGN OF 2.56GHZ PHASE LOCKED LOOP

Abstract

The interest in frequency synthesizers has increased significantly in recent years due to the swift advancements in the fields of wireless communication and radio frequency. A frequency synthesizer generates frequency by acting as a local oscillator (LO). Our goal in this research is to investigate the use of various architectures for high-frequency (wireless band) generation in CMOS technology. The voltage-controlled oscillator (VCO), frequency divider, and charge pump are the three most power-hungry blocks in a frequency synthesizer and account for the majority of the total power consumption due to their high-frequency operation. These circuits are the bottleneck to achieving the aforementioned goal. When it comes to noise, the VCO is the most important block overall. Phase noise and spurious are the two non-idealities in the frequency synthesizer manly. Phase noise can be defined as the ratio of noise power to carrier power, while spurious noise originates from power supply variations and charge pump leaks. The 2.56GHz band is intended for PLL. It is simulated using 65nm technology. In the vast field of frequency synthesizer applications, noise is a critical problem. But there are two quite distinct sides to noise.The Frequency synthesizer is employed in a first class of applications to extract weak signals from very noisy environments. One of the main uses for a frequency synthesizer is to generate an output signal that is multiple of the reference signal at a different frequency. In this case, the reference signal is noise-free, but the frequency synthesizer circuit introduces noise. The frequency synthesizer loop filter and phase frequency detector are designed to fit both trade-offs in order to provide the best performance for a given application. The trade-off in the frequency synthesizer is that as the loop bandwidth increases, the lock time will decrease but the spur level will increase.