DESIGN OF CONTINUOUS TIME AUDIO ANALOG TO DIGITAL CONVERTER WITH ASYNCHRONOUS PASSIVE NOISE SHAPING SAR QUANTIZER

Abstract

This thesis discusses the Design of Continuous Time Audio Analog to Digital Converter Design with Asynchronous Passive Noise Shaping SAR Quantizer. The proposed SAR ADC architecture comprises a 3-bit switched-capacitor DAC array, residual Block, Strong Arm Latch comparator, clock generator block, and a digital control unit. The switched-capacitor digital-to-analog converter (CDAC) has one extra capacitor added for residual calculations. The digital control unit generates the reference voltage and controls the SAR logic and the output buffer. The ADC is designed using a TSMC 180nm process technology node.Simulation results show tha tthe suggested ADC operates at a sampling rate of 6.144MS/s.The simulation yielded a signal-to-noise ratio (SNR) of 110 dB over a bandwidth of 24kHz. Additionally, I have also worked on investigating the performance of Strong Arm latched comparator using the 28nm FDSOI BSIM model and observed how its offset and delay vary with temperature. The same was extended to seven stages Ring oscillator.The frequency of oscillation variation at cryogenic temperatures is documented.