SIGMA DELTA MODULATOR FOR LOW POWER ADC APPLICATIONS

Abstract

Analog and digital signals are crucial in electrical engineering and modern technology. As electrical and computer engineers delve into developing new technologies, understanding the utilization and representation of these signals is paramount. Due to limitations of analog signal, accurate and efficient conversion to digital form for processing is necessary. The analog to digital converter is responsible for taking an analog input signals (voltage or current) and producing a digital representation based on a defined number of bits, or resolution. This thesis analyzes and design of a Second order Discrete-time Sigma Delta modulator for low-power applications. The demand for low-power applications is growing, particularly because the RF component of a circuit is among the most power-intensive. Therefore, an ADC that consumes minimal power is essential. Over the past decade, discrete-time ΔΣ modulators have gained popularity due to their suitability for low-power applications and efficient architecture. The second-order modulator is designed to operate within a signal band of 24 kHz, with an oversampling ratio of 64 and clock frequency of 3.072 MHz. It achieves a signal-to-noise ratio (SNR) of 67.6 dB and consumes 0.59mW of power, making it suitable for many low-power and portable applications. The circuit simulation was performed using a 180nm CMOS process, demonstrating its feasibility for integration into modern semiconductor technologies. In addition to the design and simulation of the ΔΣ modulator, this thesis explores various design challenges, such as noise shaping, quantization noise reduction, and power efficiency optimization. Detailed analyses of the modulator’s performance metrics, including linearity, dynamic range, and power consumption, are provided. Comparative studies with existing ADC architectures highlight the advantages and potential trade-offs of the proposed design. The findings of this work contribute to the ongoing efforts to develop efficient and low-power ADCs for applications in wireless communication, medical devices, and other fields that require high performance with minimal energy consumption. Future research may involve the implementation of the modulator in a physical prototype and testing in real-world scenarios to further validate its performance and reliability.