PARALLEL PIPELINING ARCHITECTURE FOR EFFICIENT CRC IMPLEMENTATION ON FPGA

Abstract

The Cyclic Redundancy Check (CRC) is an essential component in the fields of data storage, com-munication systems, and networking environments as it is used for error detection. One of the current challenges is to ensure efficient data transmission speed while making the most of hard-ware resources. Consequently, the calculation of CRC has become a bottleneck in system imple-mentations. This thesis aims to create and execute CRC-3 systems specifically tailored for GSM Communication systems, with a focus on error detection. To achieve high throughput data and op-timal utilization of hardware resources, a parallel pipelining method is employed to implement the CRC architecture for both the CRC encoder and decoder systems. The CRC-3 error detection sys-tem is designed and implemented. The Very High-Speed Integrated Circuit Description Language (VHDL) is utilized for coding purposes. The entire architecture undergoes functional simulation and verification using the Xilinx ISE 14.7 simulator.