NANO-AES IMPLEMENTATION FOR RESOURCE CONSTRAINED IOT DEVICES

Abstract

With the advancement of internet technology, the number of internet-connected devices is con-stantly growing. Consequently, the information transmitted through electronic channels faces the risk of security breaches. To safeguard this information, it is crucial to employ encryption methods for data transmitted over the internet. However, due to hardware limitations, encrypting data solely through software becomes impractical. This thesis introduces an FPGA implementation of an area-efficient Nano AES encryption algo-rithm. AES is a symmetric cryptography algorithm widely recognized for its high level of security, particularly for IoT devices. The proposed architecture incorporates an 8-bit data path and utilizes an existing S-box for both encryption and key expansion stages. To minimize the required area, the shift rows operation is integrated into the state register. Additionally, the substitute bytes operation is achieved through a ROM-based LUT structure. The mix columns operation, using four internal registers, is designed to accommodate an 8-bit data path, further optimizing the area. This ap-proach is particularly suitable for IoT applications, aligning with the primary objective of reducing area requirements.