Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/1815
Authors: Dubey, Rahul
Issue Date: 2005
Abstract: Design methodologies for motor control systems are changing with different hardware platforms available to designers. In the 1980's motor drive controllers were designed using microcontroller hardware, which operated on interrupt driven single threaded architectures. Several deterministic sections of motor control like speed, current measurement, generation of gating signals for power devices, and protection were coded in processor specific assembly language to obtain repeatable response times. With increasing use of motion controllers in myriad applications, custom chip architecture for motor control is finding way into the market place. Application specific chips catering to different aspects of motor control - Pulse Width Modulated (PWM) control signal generation, speed measurement with user programmable parameters are complementing microcontroller based designs. In the 1990's Digital Signal Processor (DSP) based Controllers designed for digital control, came out with lots of onboard hardware functionality and started replacing the microcontroller in motor control applications. Unlike the microcontroller , the DSP controller offered much faster single threaded operation and had architectures to quickly compute parameters for sensorless or vector control operations. The only drawback of the DSP Controller based system was its inability to cater to custom motor control designs, where single chip controlled multi-axis or motor operations are desired. Its onboard hardware peripherals - timers, comparators , capture units for triggering on an event, PWM ( Pulse Width Modulation) logic circuit, Quadrature-Encoder-Pulse (QEP)circuits , General Purpose Bidirectional Digital I/O (GPIO) pins and interrupt logic fall short when catering to multi axis control architectures. The availability of high density Programmable Logic Devices (PLDs) has opened an option of using concurrent processing ability to offset the limitations posed by the conventional DSP. Contemporary motor drives use programmable logic technology based dedicated motor control components, which can either interface to a DSP based controller or a processor. Examples of such reported components include architectures for speed measurement, current control and Space Vector Pulse Width Modulation (SVPWM) generation. Some work has also been reported on complete drive control architecture using programmable logic. But there has been a lack of on-chip re-usability approach for the existing PLD based motor components. The purpose of this work on motor chip architecture is to propose an electrical drive control library, giving reprogrammable hard-wired deterministic response times in hardware domain. For this a clear demarcation is made , where the software based nondeterministic tasks for computation of trajectory , speed and acceleration profile is left to the general purpose processor and tasks on parameter measurement, firing circuit , lock-out delay and protection is done by the proposed blockset. Some inherent benefits of a Hardware Description Language (HDL) designed library based on reprogrammable hardware like Field Programmable Gate Array (FPGA) provides for a function library which is hardware independent, allows for concurrent processing, can contain easily integrate able motor functions blocks, make use of contemporary on-chip resources on PLD and have a set of customizable parameters for setting up custom applications. Concurrent processing ability makes feasible, realization of multi-motor or multi-axis single chip systems. In this work each motor control block is analysed in terms of the system resources it takes - logic and memory. Typical input , output , initialization and configuration parameters for each block are discussed along with its instantiation. The proposed electrical drive library blocks, once interconnected directly accepts system feedback using standard on chip General Purpose Input Output (GPIO) and reference signals either from standard on chip GPIO or from on-chip processor in a System on Programmable Chip (SoPC) environment. From the motor control system feedback functionality viewpoint, axis position, motor current and motor speed is considered. Independent digital logic blocks running concurrently are used for measurement of these parameters. Motor speed measurement logic block takes input from an incremental encoder and computes motor speed, position and direction. The speed measurement logic is capable of detecting speed feedback from high resolution encoders. Similarly an ADC scan digital block updates current registers with help of configurable current loop update time. The axis position is measured, by a hardwired logic which converts absolute gray code position to binary data. System protection logic consists of several components. The other components include current overload and configurable dead-time control. For control of motor position, velocity and current loops , two types of controllers with configurable update times have been designed using hardware logic . A velocity mode control algorithm has been used for designing the Proportional Integral (PI) controller , which also provides for anti-windup control. The other controller is a Fuzzy controller ii i which is designed for use, when detailed knowledge of the process is not known. The fuzzy controller's fuzzification block is based on a triangular membership function and the defuzzication block uses mandani's minimum rule and height method for finding out change in controller action. Digital logic for controlling power devices has been designed for three types of bridge configurations. Afiring angle controller for a fully controlled three phase converter based on zero crossing angles of line voltages is synthesized and experimentally verified. Similarly control of voltage and frequency of three phase Inverter Bridge is implemented using SVPWM modulation technique. A torque controlled Permanent Magnet Synchronous Motor (PMSM) drive is prototyped using measurement, transformation of variables and hysteresis current controlled function blocks. To ease the use of motor control integration in System on Chip (SOC) applications, the motor drive library components are integrated to form a complete drive and encapsulated as a peripheral , which is connected to an industry standard SOC bus. The SOC processor has access to different drive parameters which it can monitor or control over the On-chip Peripheral Bus (OPB). Contemporary co-ordinated multi-drive system consist of a Programmable Logic Controller (PLC) where the drive setpoints are calculated and sent to the drive either using a hardwired 4-20 mA loop or proprietary industry standard bus like Profibus, DeviceNet, Modbus . The concept of putting one or multiple drives on a chip brings the hardware integration technology to a new scale. The soft non-deterministic processing load of a PLC and deterministic update time for drives are now merged into one component. Verilog Hardware Description Language (HDL) based re-usable re-targettable blocks proposed in this work have been verified experimentally by creating a complete drive system. Xilinx SPARTAN II® Field Programmable Gate Array (FPGA ) consisting of 200,000 gates has been used for testing of all drive control blocks. A12 bit Analog Digital Converter (ADC) and Digital Analog Converter (DAC) are interfaced with FPGA to connect to drive analog signals. Xilinx software suite consisting of Integrated Synthesis Environment (ISE)® , Embedded Design Kit ®(EDK) , System Generator and ChipScope® have been used to verify , create and download FPGA design files written in Verilog Hardware Description Language. Two different drive systems have been created to verify working of a Space Vector PWM technique and torque regulated drive control using digital hysteresis control. Experiments carried out using HDL-PLD based control in blocks demonstrate the ease and benefits of rapid prototyping of drive systems using HDL-PLD based library of motor control blocks. To summarize, a electrical drive control reprogrammable hard-wired logic is proposed, which is used to create two customized motor control schemes. Various components of this library include feedback, control and power device triggering circuits. The electrical drive library blocks use concurrent operation, which makes possible single chip based multi-motor or multi-axis control. These blocks can also be integrated to form a drive peripheral which can attach to SOC bus architectures. This way software tasks results can be passed to the hardware tasks of the drive. Experimentation on prototyping Induction Motor and PMSM motor based control schemes has been carried out using the proposed drive control function blocks.
Other Identifiers: Ph.D
Research Supervisor/ Guide: Agarwal, Pramod
Vasantha, M.K.
metadata.dc.type: Doctoral Thesis
Appears in Collections:DOCTORAL THESES (Electrical Engg)

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