TECHNIQUES FOR IMPROVING LEAKAGES AND ROW HAMMER FAILURE IN NANO-SCALE DRAM TRANSISTOR

Abstract

In the last two decades, the chip density and speed of dynamic-random-access-memory (DRAM) have improved tremendously by 128X and 20X, respectively, due to continuous scaling of the DRAM technology. The DRAM holds about 53% of the memory market due to the wide range of applications in computers, smartphones, digital electronics, high-speed networks like servers, routers, and switches, etc. The saddle-fin-recessed-channel-access-transistor (S-RCAT) is the device in use for the cutting edge DRAM nodes due to its superior leakage immunity and scalability. In this thesis, we investigate and analyze the various novel techniques to enhanced performance and reduced leakage in S-RCAT DRAM. We begin the work by the calibration of our simulation setup with the experimentally reported data using the Sentaurus TCAD tool for the accurate and reliable prediction of the TCAD results. We identify three high-value-problems that contribute to the performance degradation of the DRAM transistor, which includes: (i) gate-induced-drain-leakage (GIDL), (ii) performance shifting due process variations in the gate stack, and (iii) cell-to-cell interference due to row hammering. To address these high-value-problems, we present a series of novel techniques. The proposed novel techniques significantly improve leakages without affecting the baseline performance of the DRAM transistor. We investigate the impact of the composite variations in gate-stack on the performance parameters of the DRAM transistor. To suppress GIDL current, a novel technique of using a dual-gate work-function in recessed-channel-access-transistor (RCAT) is proposed. The GIDL current is believed to be the most dominant off-state leakage in the DRAM transistor, which increases the refresh rate of the cell. We investigate the GIDL current dependency on the different dual-gate configurations of RCAT. Using the dual-gate technique, we achieve GIDL current reduction significantly without affecting the high threshold voltage of the DRAM transistor.