SYSTEM LEVEL ARCHITECTURES AND OPTIMAL MAPPING FOR RECONFIGURABLE COMPUTING

Abstract

Reconfigurable computing is a new paradigm that evolved from the advance ment of VLSI fabrication technology. Reconfigurable computing systems (RCSs) promise to be a valuable alternative to the conventional computing systems such as micro-processor based systems and application specific integrated cir cuits (ASICs). In RCS the hardware can be dynamically reconfigured during the runtime. The best way of meeting real-time system requirement is by im plementing embedded systems with hardware programming at run-time using reconfiguration. To exploit the potential of the RCS, suitable methods for RCS design, RCS architectural design, tools for doing reconfiguration at run-time, effective techniques for scheduling and mapping of design library on the recon figurable logic units etc. are required. This work addresses these problems and provides a generalized methodology for reconfigurable embedded computing sys tem (RECS) design. An algorithm for optimization of system level architecture has proposed, the design and development of parameterized module scheduling and mapping algorithms have been carried-out. The first part of the thesis work aims to provide an integrated design method ology for designing a reconfigurable embedded computing system (RECS). For a given application specification or application code in C/C++ with given con straints, a RECS can be designed following the proposed method. Indeed, in this thesis a reconfigurable application specific instruction-set processor (RASIP) for software defined radio (SDR) has been implemented based on the proposed methodology. System partitioning has been done based on evolved architec ture. At present manual system partitioning has been considered for hardwaresoftware partitioning and parameterized module based scheduling and mapping algorithms have been developed. The algorithm integrates the design library mapping onto the reconfigurable logic units (RLUs) and schedules the tasks in the directed acyclic graph (DAG). Reconfigurable hardware in the system ariii Abstract chitecture is termed as (RLU). Methodology includes procedural steps for doing automatic program analysis. Further an algorithm has been proposed for archi tecture optimization. Efficient algorithms have been developed for scheduling and mapping of the resources. Our methodology incorporates new concept of variable size area of reconfigurable logic units (RLUs), and each node (task) of the DAG has been implemented with various versions, so that for executing a task, depending upon the RLU area size, a suitable version of the implementa tion is selected from the pre-defined storage location. This kind of design of task implementation is called parameterized module based design. The developed al- gorithms achieved the performance gains from 13.90% to 39.74% and hardware utilization efficiency gain varies between 12.5% and 46.67%. The real param eters such as reconfiguration delay and division of RLUs have been considered (Virtex-II Pro (XC2VP30 /XC2VP50) and Virtex-4 (XC4VLX25)). The second part of this work carries the design and development of reconfig urable application specific instruction-set processor (RASIP) for software-defined radio (SDR). The RASIP for SDR has been designed as a case study to prove our methodology. Normally, system design methodology analyzes the embed- ded computing domain to present the target architecture. Based on functional requirement, the architecture has been proposed depending upon the hardware resources availability. Commercially available system-on-chip like platform based FPGAs with reconfiguration technology have been considered for the implemen tation of task. It includes the design of efficient architecture for the RASIP for SDR, design of instruction-set, design of control logic, and integration of these RASIP modules. In this work, the flexibility of user-defined instructions is unique and novel in contrast to the existing instruction-sets of the processor or application specific instruction-set processors (ASIPs). In RASIP, as a program- ming model two methods are proposed, one is simple architecture with embedded CPU, where CPU takes care of data I/O, context (design library in the form of bitstreams or configuration data) loading and control of RLUs. Another method is the architecture without CPU, instruction-set designed like VLIW instruction form by making the architecture like RASIP. With respect to the compilation technology, the intelligent scheduling and mapping methodology is used based on parameterized design library task mapping onto the RLU as well as fixed hard ware. Proper care has been taken to ensure that the proposed methodology can be used independently with developed algorithms and techniques. The design of iv Abstract RASIP for SDR is first of its kind. The same principles can be easily extended to other applications. The third part of this work presents the design of the parameterized modules of RASIP for SDR. Each module has been designed with more than one version of the implementation and each version may be different in granularity or hard ware requirement and its execution time. Simulation of functional verification for CDMA IS-95 forward and reverse traffic channels except quadrature phase shift keying (QPSK) modulator and demodulator has been done, satisfactorily and hardware estimation has been carried-out using Xilinx ISE. In addition, pa rameterized modules designs have been carried-out for Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) filter. The fourth part deals with the integrated design and simulation environment that integrates all the system level tools in a single environment. This includes design of all the RASIP modules using SystemC to support both hardware and software design, modeling, and verification in a single environment. The designed models have been synthesized using SystemCrafter (SC) tool. VHDL implemen tation of Partial modules has been done (such as convolutional encoder, long code generator, Walsh generator, FFT, and FIR filter are implemented on stan dard and commercially available FPGAs). The proposed framework enables the use of System Generator, MATLAB, SystemCrafter, all in a single environment so that the design, modeling, simulation, and verification of the complex system is simplified in design time as well as simulation time at system level. Transac tion level modeling (TLM) of CDMA IS-95 forward traffic channel has also been carried-out. Lastly, the summary of the total contributions are given and scope of the future work is outlined.