DELAY AND CROSSTALK ANALYSIS FOR A CMOS DRIVEN GLOBAL INDUCTIVE VLSI INTERCONNECTS

Abstract

Aggressive scaling of semiconductor process technology over the last several decades has resulted in creation of many new products, such as computers, camera, cell phones and information appliances. The trend is expected to continue for the coming years and create countless opportunities and challenges. Recent developments in semiconductor industry show a rapid increase in chip frequency and design complexity. Introduction of newer technologies is now moving towards a two year cycle as compared to traditional three year cycle. Though technology scaling helps in addressing design complexity and performance trends, it opens up a whole new spectrum of design validation challenges. As technology scaling trend continues, interconnect parasitics play dominant role in determining chip performance and functionality. RLC delays become significant portion of chip delay and noise/crosstalk caused due to parasitic coupling poses threat to circuit functionality. The intense drive for signal integrity has been at the forefront of rapid and new development in CAD algorithms. With increasing demands for high signal speeds coupled with decreasing feature sizes, interconnect effects such as signal delay, distortion and crosstalk become the dominant factors limiting overall performance of high-speed systems. If not considered during the design stage, interconnect effects can cause failed designs. Since extra iterations in the design cycle are costly, accurate prediction of these effects is a necessity in high speed designs. Recently, various analytical approaches have been proposed for predicting propagation delay through an interconnect and crosstalk between coupled interconnects. Many of these analytical works have modeled the CMOS-driver gate by a linear resistor in the driver-interconnect-load model. Such an approach leads to discrepancy in results. The linearization of the transistors results in an inaccurate estimation of interconnects effects. This can be understood by noting that a transistor in a CMOS gate operates partially in the linear region and partially in the saturation region during switching. In the linear region, the transistor can be accurately approximated by a resistor. However, in the saturation region, the transistor is more accurately modeled as a current source with a parallel high resistance. The Thevenin equivalent of this circuit is a voltage source with a high resistance in series. Thus, modeling CMOS gate by a single resistor will result in inaccurate estimations. It is therefore important to use a more accurate gate model, for determining time delay, peak overshoot and crosstalk, in a driver- interconnect-load system. In this thesis, an improved analytical model is developed for determining propagation delay and crosstalk in inductive long interconnects. The model combines distributed RLC interconnect - equivalent with the well established Sakurai's Alpha power law model for the MOS transistors. It has been amply demonstrated in literature that for short channel transistors, Alpha-Power MOS model overcomes the shortcomings of previously used models. Since the model is simple, it can be easily applied in sub-micron MOS - circuit analyses. Therefore, applying Alpha power law model for the transistors of CMOS-driver and a suitable RLC model for the interconnect, a composite driver-interconnect-load (DIL) model is developed for the analyses carried out subsequently. The composite DIL-model is applied for analytically estimating propagation delay and generating waveform at far and near ends of the RLC interconnect. The distributed RLC interconnect is represented by an equivalent 7t-model. The two different cases of slow and fast input ramps are considered. For either case, the model gives an insight into four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. It is shown that by this method voltage waveform at each point of an interconnect can be obtained analytically. The analytical results for the output voltage waveform and propagation delay are compared to SPICE simulations. The analytically calculated 50% propagation delays and voltage waveforms at both ends of interconnect are in very good agreement with SPICE simulation results. in The issues associated with signal integrity (SI) have drawn major attention of interconnect designers in high-speed digital VLSI/SoC designs. As signal integrity analysis become far more important, the need for viable methodologies and solutions, addressing these critical issues, is more pressing than ever. In order to have a good understanding of the problem of crosstalk its dependence on various signals and interconnect parameters are studied through SPICE simulations. The study includes crosstalk noise due to presence of mutual parasitic interconnect inductance and capacitance. It is observed that crosstalk is affected by transition time of the signal, length of interconnect, distance between interconnects, size of driver, pattern of input, and line parasitics. The crosstalk noise takes its worst form for low transition time; medium/ long length interconnect; the two coupled lines switching in opposite direction. Functional crosstalk noise is analyzed for a CMOS driven capacitively and inductively coupled interconnect. A transmission line based coupled model of interconnect is included in the composite DIL model. Using this model, a transient analysis of crosstalk noise is carried out for slow and fast input ramps. Comparison of the analytical results with SPICE extracted results shows that the average error involved in estimating noise peak and their time of occurrence is less than 7%. The proposed model is also compared with a well known and commonly used model, which represents a CMOS gate by a linear resistance. Significant improvements are observed in terms of prediction of crosstalk noise waveform, positive and negative peaks, and their time of occurrence. The dependence of peak noise on driver width of aggressor (active) line is also analyzed. The positive and negative peaks increase with increase in driver width. The composite DIL model is further used for crosstalk analysis in simultaneously switching scenario. Waveforms are analyzed for the cases when the inputs to two coupled interconnects are switching in-phase and out-of-phase. For inphase switching condition fast and slow input ramps are considered, where for each case the CMOS has to pass through four regions of operation. For out-of-phase switching, only fast input ramp case is analyzed, where the CMOS drivers of IV aggressor and victim lines have to pass through ten regions of operation. The output of the analytical model matches closely with the SPICE simulation results. The computational errors involved (yvrt SPICE) for analytically calculated propagation delay and peak voltage under in-phase and out-of-phase switching are nominal. The performance of DIL model is compared with that of the model using linear resistive driver. It is observed that modeling of non-linear CMOS gates by their equivalent linear region resistance can lead to erroneous estimation of waveform shape, noise peak, timing instant of noise peak occurrence and transition time delay. Compared to resistive driver, the noise peaks and their timings are more effectively predictedby the proposed DIL model. An analysis to study the effect of repeater insertion on crosstalk between adjacent interconnects is carried out. Power dissipation and propagation delay in a crosstalk aware environment are also considered. The analysis shows that repeater insertion not only reduces the propagation delay, but also crosstalk levels for coupled lines. This is achieved at the cost of a marginal increase in power dissipation. The analysis leads to a new criterion for repeater loaded coupled interconnects. It shows that instead of the commonly used power-delay-product (PDP) criterion, a powerdelay- crosstalk-product (PDCP) criterion suits better for the determination of optimum number of repeaters for overall minimization of delay, power and crosstalk. The research work indicates that accurate estimation of propagation delay and crosstalk noise during initial design cycles can lead to efficient design of high performance systems. It also emphasizes that the judicious study of performance parameters, particularly crosstalk can be extremely effective in guiding noise aware physical design optimizations. The results of the present investigations can be very useful in designing of crosstalk aware high-speed low-power VLSI circuits, which is an immediate requirement in modern portable electronic gadgets.