Please use this identifier to cite or link to this item:

`http://localhost:8081/xmlui/handle/123456789/1789`

Title: | ANALYTICAL STUDY OF CMOS-SUBTHRESHOLD OPERATION FOR LOW POWER VLSI APPLICATIONS |

Authors: | Jharia, Bhavana |

Keywords: | ELECTRONICS AND COMPUTER ENGINEERING;CMOS-SUBTHRESHOLD OPERATION;LOW POWER VLSI APPLICATIONS;VLSI CIRCUITS |

Issue Date: | 2007 |

Abstract: | In recent years, there has been increasing prominence of portable battery operated low power systems such as hearing aids, pacemakers, cell phones, pagers, and portable computers become more complex, prevalent, and demand increased battery life. Therefore, the demand for increased battery life will require designers to seek out new technologies and circuit techniques to maintain high performance with longer battery lifetime. Portable devices, however, are not the sole motive behind the low power and low energy design efforts. The increasing power dissipation for fixed supply devices is almost equally challenging as for portable devices. As technology feature size is reduced, the number of transistors on the chip is increased and more power is dissipated. The main components of power dissipation are switching power and leakage power. Switching power, being the dominant power component, has caught special attention in recent years. Many techniques have been introduced to control this ever-increasing power component on all levels of design abstraction. Increased leakage current due to technology feature downsizing is another challenge that faces circuit designers in the VLSI and ULSI era. In the VLSI circuits a large number of MOSFETs are often simultaneously biased in the subthreshold region of operation due to ultra-low power consumption with moderate performance degradation. In such a situation, the subthreshold currents due to the individual devices add up to a source of substantial power dissipation. This power dissipation is highly undesirable, as it causes many reliability problems. In submicron devices the problem is further aggravated by the high electric field existing in the channel region. Under the influence of high electric field the carriers multiply by impact-ionization. The result is an increased drain current. In this thesis, an analytical approach is developed to analyze effect of scaling and impact ionization in submicron and deep submicron MOSFETs. To include the effect of impact ionization on drain current, multiplication factor is first determined using well-established expressions. The analysis shows that for subthreshold operation it is important that the effect of impact ionization should be included in the analytical expression for drain current. Calculations show that multiplication factor increases with drain-source voltage, VDS, and gate voltage and decreases with increase in gate oxide thickness. Calculations also show that multiplication factor increases with increase in drain/source pn-junction depth. However, multiplication factor levels off at larger junction depths. Shallower junctions are therefore desirable if carrier multiplication is to be restricted. Present study considered Fjeldly and Shur's physical model for subthreshold current. While this model yields accurate results for submicron devices, it does not take into account the effect of impact ionization, which is more prominent in devices of nanometer channel length. The subthreshold current model of Fjeldly and Shur is therefore, first modified to include the effect of impact ionization, for all analytical purposes. The modified current model agrees well with results obtained from ATLAS simulation. It shows that impact ionization increases subthreshold current by few percents. Such an increase in subthreshold current model, the DIBL -coefficient was reconsidered. It has been found that this parameter is not independent of the terminal voltages of a MOSFET. The DIBL- coefficient has a strong dependence on VDS and relatively lesser dependence on gate-source voltages VGS. This analysis shows that, because of the strong VDS dependence of the DIBL-coefficient, the threshold voltage shift is a non-linear function of VDS, in contradiction to a constant DIBLcoefficient as assumed previously. It is also found that DIBL- coefficient increases with increase in channel length and decreases with increase in temperature. Effect of scaling methods on the subthreshold conduction of a small geometry device is also analyzed. The results show that as the channel length is scaled down, multiplication factor increases slowly in the higher regime of channel length. In the lower regime of channel length, multiplication factor rises rapidly. This result also justifies the inclusion of impact - iii ionization effect on subthreshold current. However, the analysis shows that there is insignificant dependence of multiplication factor on the method of scaling. Constant electric field scaling produces the largest threshold voltage shift due to DIBL. Selective scaling has the least DIBL, with generalized scaling produced DIBL falling in between the two extremes. Finally in this thesis, an analytical approach is developed to obtain optimal VDD for minimizing total power dissipation. It is well known that in above threshold CMOS operation, a tradeoff exists between propagation delay and power dissipation, when voltage is scaled. When the supply voltage is scaled down to reduce power dissipation, propagation delay is increased. SPICE simulation, however, shows that this does not hold good for subthreshold logic. For a threshold CMOS- logic operation, propagation delay in most cases first increases and then decreases with supply voltage scaling. The subthreshold current model mentioned above is used to calculate voltage dependence of propagation delay of a CMOS inverter. The results thus obtained show that, the delay increases with increase in supply voltage. An important requirement of a logic circuit is symmetric input-output characteristics. The ratio of pMOS and nMOS widths that meets this requirement is determined using the modified subthreshold current model. The ratio thus obtained is primarily mobility dependent, as in the case of above threshold logic operation. The analytical model presented shows very well match with SPICE simulations. The results of the present investigations can be very useful in designing low power VLSI circuits, which is an immediate necessity in the modern portable electronic gadgets. |

URI: | http://hdl.handle.net/123456789/1789 |

Other Identifiers: | Ph.D |

Research Supervisor/ Guide: | Agarwal, R. P. Sarkar, S. Handa, S. C. |

metadata.dc.type: | Doctoral Thesis |

Appears in Collections: | DOCTORAL THESES (E & C) |

Files in This Item:

File | Description | Size | Format | |
---|---|---|---|---|

ANALYTICAL STUDY OF CMOS-SUBTHRESHOLD OPERATION FOR LOW POWER VLSI APPLICATION.pdf | 69.71 MB | Adobe PDF | View/Open |

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.