ANALYTICAL STUDY OF CMOS-SUBTHRESHOLD OPERATION FOR LOW POWER VLSI APPLICATIONS

Abstract

In recent years, low power circuits are gaining prominence due to use of portable battery powered devices such as hearing aids, pacemakers, cell phones, pagers, and portable computers. Therefore, the demand for increased battery life has compelled designers to seek out new technologies and circuit techniques to maintain high performance with longer battery lifetime. As technology feature size is reduced, the number of transistors on the chip is increased and circuits dissipate more power. The main factors of power dissipation are switching power and leakage power. Switching power, being the dominant power component, has caught special attention and many techniques have been developed to control the ever-increasing power component on all levels of design abstraction. Increased leakage current due to technology feature downsizing is another challenge faced by circuit designers in the VLSI and ULSI era. In the VLSI circuits a large number of MOSFETs are often simultaneously biased in the subthreshold region of operation due to ultra-low power consumption with moderate performance degradation. In such a situation, the subthreshold currents due to the individual devices add up to a source of substantial power dissipation. This power dissipation is highly undesirable, as it causes many reliability problems. In submicron devices the problem is further aggravated by the high electric field in the channel region. Under the influence of high electric field the carriers multiply by impact-ionization. The result is an increased drain current. In this thesis, an analytical approach has been developed to analyze the effect of scaling and impact ionization in submicron and deep submicron MOSFETs. To study the effect of impact ionization on drain current, multiplication factor is first calculated using well-established expressions. The analysis shows that in the subthreshold region, effect of impact ionization should be considered in the analytical expression for drain current. Calculations show that multiplication factor increases with drain-source voltage & gate voltage and decreases with increase in gate oxide thickness. Calculations also show that multiplication factor increases with increase in drain/source pn-junction depth. However, multiplication factor levels off at larger junction depths. Shallower junctions are therefore desirable if carrier multiplication is to be restricted. In the present study, Fjeldly and Shur's physical model has been considered for calculating subthreshold current. This model yields accurate results for submicron devices but does not take into account the effect of impact ionization, which is more prominent in devices with nanometer channel length. The subthreshold current model of Fjeldly and Shur has been modified to include the effect of impact ionization for all analytical purposes. The modified current model agrees well with the results obtained from SPICE simulation. Results indicate that impact ionization increases subthreshold current by few percents. Such an increase in subthreshold current model, the DIBL -coefficient was recalculated. It has been observed that DIBL -coefficient is not independent of the terminal voltages of the MOSFET. The DIBL- coefficient has a strong dependence on drain-source voltage and relatively lesser dependence on gate-source voltages. This analysis shows that, because of the strong drainsource voltage dependence of the DIBL-coefficient, the threshold voltage shift is a non-linear function of drain-source voltage, in contradiction to a constant DIBL-coefficient as assumed previously. It is also found that DIBL- coefficient increases with increase in channel length and decreases with increase in temperature. The effect of scaling methods on the subthreshold conduction of a small geometry device has also been analytically studied. The results show that as the channel length is scaled down, multiplication factor increases slowly in the higher regime of channel length, which in the lower regime of channel length, multiplication factor rises rapidly. This result also justifies the inclusion of impact - ionization effect on subthreshold current. However, the iii analysis shows that there is insignificant dependence of multiplication factor on the method of scaling. Constant electric field scaling produces the largest threshold voltage shift due to DIBL. Selective scaling has the least DIBL, which generalized scaling DIBL varies in between the two extremes. Finally, an analytical approach has been developed to obtain optimal supply voltage for minimum total power dissipation. Literature survey shows that in above threshold CMOS operation, a tradeoff exists between propagation delay and power dissipation, when supply voltage is scaled. It has been observed that when the supply voltage is scaled down to reduce power dissipation, propagation delay increases. SPICE simulation, however, shows that this does not hold good for subthreshold logic. For a threshold CMOS- logic operation, propagation delay in most cases first increases and then decreases with supply voltage scaling. The subthreshold current model discussed above has also been used to study voltage dependence of propagation delay of a CMOS inverter. The results show that the delay increases with increase in supply voltage. The ratio of pMOS and nMOS widths of a symmetric circuit has been calculated using the modified subthreshold current model. The ratio is primarily mobility dependent, as in the case of above threshold logic operation. The analytical model presented shows a good match with SPICE simulations. The results of the present investigations can be used to design low power VLSI circuits to meet the requirements ofthe modern portable electronic gadgets.