Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/1780
Authors: Chandel, Rajeevan ( Nee Pathania)
Issue Date: 2005
Abstract: In recent years, very large scale integrated chips find numerous applications in electronic circuits. With continuous sophistication in very large scale integration (VLSI) technology, as more and more functionalities are integrated, the chip size is on the increase. Thus, long interconnects have become common onchip features. It has become well accepted that interconnect delay dominates gate delay in current deep submicrometer (DSM) VLSI circuits. The long interconnects cause undesirable effects viz (i) high propagation delays (ii) degradation of the signal waveforms (iii) enhanced short circuit power dissipation and (iv) increased switching power dissipation. Therefore, there arises a needto mitigate these detrimental effects. In the last decade, there has been an increasing prominence of portable battery operated low-power systems. It has been observed that large interconnect loads result in excess power dissipation and propagation delays. In addition to this, the use ofrepeaters to reduce delay also causes an undesired increase in power dissipation. Power dissipation is therefore, another important concern of VLSI design. Several techniques and methodologies have been developed for minimizing the propagation delay and the power dissipation in VLSI circuits, over the years. Voltage-scaling has been an important technique for low power VLSI design, as the power dissipation is directly proportional to square of the supply voltage, but it adversely affects delay. In view of the above a tradeoff between delay andpower dissipation is the need of the day. For driving large interconnect loads, a single buffer is not an ideal solution. Therefore, repeater insertion i.e. a number ofbuffers placed at regular interval ofdistance in long interconnections has emerged as a technique for delay reduction. Various techniques have been developed to design repeater chains for delay and power minimization, a good understanding ofthe influence ofscaled-voltage environment for low power dissipation on such systems is still wanting. In this thesis, an analytical approach is developed for determining the optimum number of repeaters to be inserted in the delay-centric design of long interconnects. Considering delay minimization by repeater insertion, the effects of voltage-scaling on delay and optimum number ofrepeaters inserted in interconnects are analysed. Analytical expressions for ninety percent delay are derived for CMOS repeater driven resistive as well as inductive interconnects. Models for MOSFET saturation drain conductance and repeater capacitance are proposed. Analysis shows that the optimum number ofrepeaters decrease with supply voltage scaling for both resistive and inductive interconnects. The results demonstrate that, for correct estimation of delay and power dissipation, it is important to take the inductive effects into account. Acompact analytical expression for the output voltage of a single CMOS repeater driven long inductive interconnects is developed. Two analytical methods of transistor channel width optimization, one for minimum delay and the other for minimum power-delay product are developed. The results ofthe analyses illustrate that the optimum widths obtained by the two methods are almost equal. An analytical method for optimal supply voltage for minimum power-delay product is also developed. Influence ofvoltage scaling on optimum number ofrepeaters and the resulting delay has been analyzed for different repeater sizes by SPICE simulation. It is seen that with increase in repeater dimensions the optimum number of repeaters increase at scaled voltages. It is observed that delay increases with voltagescaling and decreases as the size ofthe repeaters increase. The effects ofrepeater size on drain saturation conductance of the MOSFETs are studied. The resulting effect of size on delay is also analysed. The influence ofdrain saturation conductance on output voltage transition ofa repeater stage, is shown by an analysis ofthe time taken for the discharge of the output voltage in an RLC interconnect load. It is shown that after a limiting threshold value of repeater dimension, the drain saturation conductance does not affect the time variations of the output voltage. As a result, there is no significant improvement in the delay ofthe output voltage. Therefore the scope ofdecreasing delay by increasing repeater size is limited. 111 Timing analysis of a repeater stage driving long interconnect loads is carried out. The output waveform ofa repeater stage and hence the delay depends on the speed ofthe input variation. As one repeater provides the input to the next repeater, these effects are further enhanced and propagated to the output. A model that takes into account such effects in a repeater chain has been developed in this thesis. Taking an interconnect as the repeater stage load, timing analyses arc carried out for resistive (7?C-modcl) and inductive (RLC-modd) interconnects. Power analysis of repeater loaded long interconnects is carried out. Switching power dissipation and the short circuit power dissipation are appreciably large in long interconnects. The short-circuit power dissipation is dependent on the rate of input transitions. Making use of the results of the timing analysis carried out, an analytical model is developed for the estimation of short-circuit power dissipation in uniform repeater-chain loaded resistive (RC) and inductive (RLQ interconnects. As the static power is much lower compared to short-circuit and switching power, it has been neglected. The results have been derived for 0.18um and 0.07um technologies and verified by SPICEsimulationresults. The research work indicates that voltage-scaled repeater insertion in long interconnects and judicious handling of the design parameters of the CMOS repeaters, can lead to the design ofhigh performance systems. It also emphasizes that the study of voltage-scaled repeaters shall be particularly important, where control of power dissipation is a stringent requirement. The results of the present investigations can be very useful in designing low-power high-speed VLSI circuits, which is an immediate requirement inthe modern portable electronic gadgets.
Other Identifiers: Ph.D
Research Supervisor/ Guide: Sarkar, S.
Agarwal, R. P.
metadata.dc.type: Doctoral Thesis
Appears in Collections:DOCTORAL THESES (E & C)

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