ROBUST NANOSCALE CIRCUIT DESIGN CONSIDERING THE IMPACT OF PROCESS INDUCED MECHANICAL STRESS

Abstract

Technology scaling, which has contributed towards the tremendous growth of silicon industry, faces several process and performance related challenges. Consequently, strain engineering has been used commensurately with physical scaling to achieve performance gain in modern CMOS processes. The process induced mechanical strain in the channel improves carrier mobility through band deformation, hand splitting, carrier redistribution, reduced scattering rate and reduced effective mass etc. Several strain engineering techniques, such as compressive/tensile Etch Stop Liner (c/t-ESL), embedded Silicon-Germanium (eSiGe) source/drain, embedded Silicon-Carbon (eSiC) source/drain, Stress Memorization Technique (SMT) etc are integrated into a state- o f-the -art C MOS process flow. 1-lowever. performance enhancement through strain engineering depends upon the volume of stressor material surrounding the channel of a device. Therefore, strain-induced performance gain depends upon various layout parameters such as source/drain length, poly-pitch, number of fingers sharing an active region, ESL boundary etc. Apart from the intentional stress sources, mentioned above, stress originating from Shallow Trench Isolation (STI) also causes a similar variability. This results into unaccounted change in the device and circuit performance. Traditionally stress-induced variability is handled by applying guardbands or performance margins to critical paths - ironically depleting the performance gains most often needed. Therefore, it is essential to model the stress induced effects so that an effective and predictable design is made possible. In this thesis, we address this problem and thereby propose a stress aware combinational circuit design methodology. Ir Layout parameters internal to a logic gate which affect the channel stress are the number of fingers of a device, gate-pitch and width of finger/device. Transistor sizing * is often achieved through increase in the number of fingers in wide width devices or through an increase in diffusion width of narrow width devices. First scenario that is considered in this thesis is when the devices have wide finger width and transistor sizing is obtained through increase in number of fingers while keeping the finger width constant. A model of Logical Effort (LE) is derived that relates the LE of an inverter with the Number of Fingers (NF) in the Multi-Finger Gate Structures (MFGS). Using this derived model of LE, a modified delay model for CMOS buffer has been proposed. It is observed that the modified buffer delay model predicts the delay more accurately. Thereafter, we optimize the value of another layout parameter internal to a logic gate, the impact of poly/gate-pitch (Lpp). It is observed that Lpp scaling results into significant performance improvement in strain engineered devices. However, the value of optimal Lpp depends upon the size of the driver and the size of the load being driven. Therefore, a model is derived for calculating optimal value of Lpp for a given size of driver and the load. Based on our observations, that the increasing NF in MFGSs degrades the performance and Lpp up scaling enhances the performance in strain engineered MFGSs, a model is derived that calculates the optimum Lpp as a function of NF in MFGSs. This model is used to equalize the logical effort of inverters used in a buffer chain and thus the delay is estimated more accurately. This also results in a significant improvement in the speed of buffers. In the study of the impact of process induced mechanical stress on MFGSs, we have assumed a plain strain condition in width direction which is valid for wide width device. Nevertheless, narrow width devices are also used in logic gates and transistor sizing is often achieved through increase in active diffusion width. Therefore. the impact of stress and Inverse Narrow Width Effect (INWE) in narrow width devices 'V and its implication on circuit design is also investigated. It is necessary to consider both these effects simultaneously while sizing the transistors. In this part of our work, an analytical model for estimating width dependent effective drive current in strain engineered devices is presented while considering both the effects. There are two width dependent effects: (a) Change in effective value of Wp/WN and (b) Non-linear change in drive capability of logic gates while using narrow width devices. We propose a buffer design methodology which considers the change in effective Wp/WN and non-linear changes in drive capabilities with inverter sizes. Our methodology results into significant reduction in buffer area and power consumption. To propose a stress-aware design methodology for combinational circuits, we need to model the impact of Layout Dependent Effect (LDE) on NAND/NOR gate performance. Series stack of transistors usually share an active region in these gates. Iherefore, the stress prolile in the channels of transistors would be different from that of a single transistor. To model delay considering stress, we first derive a nominal delay model for NAND/NOR gates. For this, a modified alpha power current model is used. We then incorporate stress-induced changes in mobility and threshold voltage of devices into this delay model. This model is then modified to derive a stress aware logical effort delay model of 2-input NAND/NOR gates. This model can now be incorporated into the method of logical effort to design combinational circuits. Using our stress aware method of LE, we improve the performance of combinational circuits No and also achieve performance predictability.