FLOW & METHODOLOGY DEVELOPMENT TO ENHANCE THE DEBUGGING CAPABILIT]ES IN 'LOGICAL EQUWALENCE VERIFICATION

Abstract

The objective of this project is to enhance the debugging capabilities in FEV flow, drawing guidelines for RTL designers and to optimize the existing FEV environment to improve the run times for SoC designs. Formal Equivalence verification (FEV) has become the main verification method for the designers and verification engineer. It's in the mainstream, as it is easy to use, integrates easily into the design flow, and finds bugs upfront than traditional simulation-based methods. As complexity of the designs is increasing exponentially, traditional debugging capabilities are time consuming. With this new work, we are going to analyze these traditional methods and identify the areas where we can improve those capabilities. This includes fixing the FEV environmental issues and provide more debugging options on failing points. During development, a low-power design undergoes numerous iterations prior to final layout, and each step in this process has the potential to introduce logical bugs. Power aware equivalency checking is an advanced method for Formal Verification from RTL to various stages till place and route. Power aware formal equivalence checking enables you to verify correct implementation of the low power designs early in the design process and decreases the risk of missed bugs, before a product goes out the door. ECO's are the inevitable steps in Soc designing. These are the last stage Engineering change orders which are have to be dealt carefully in a restricted period of time. There are a few criteria to successfully implement a functional ECO. This project discusses the ECO challenges and reviews the criteria for a successful functional ECO solution. It also consolidates the ideas that will help to solve the issues that happen during a functional ECO. A successful ECO is not only measured based on the functional equivalence with the new RTL but also on the quality of the ECO changes made. If the ECO tool inserts a lot of new logic in the converged netlist resulting in routing congestion and timing issues, it may not be possible to implement the ECO though the final netlist passes Functional Verification (FV).