ANALYSIS OF Si-NANO WIRE GATE ALL AROUND MOSFET AND ITS DESIGN ISSUES IN DIGITAL LOGIC

Abstract

At 22nm and below technology nodes, novel 3D device structures such as fin and nanowire (NW) MOSFET are considered as possible replacement. The nanowire transistors have the best scaling potential, and hold high potential for future CMOS technology generations. There have been many experimental and modelling studies, mostly at the device level, demonstrating NW MOSFET's excellent performance. However, the fabrication process complexity and very fine geometries of NW devices require many cycles of optimisation, which also necessitate large financial and time investments. As a consequence, the progress in investigating detail NW MOSFET circuit level performance, and the associated issues is relatively slow. Also, being a new technology, the reliability of NW MOSFET is under active research, in particular their response to radiation exposure needs to be investigated and analysed. The use of TCAD can help to reduce design cycles and optimise cost, as well as provide crucial insight into the issues involved. In this thesis, we investigate Si NW CMOS device and circuit level issues using well calibrated 3D TCAD process, device and circuit simulation framework for 22nm and below technology nodes. The devices are implemented using CMOS compatible lateral NW process using top down approach. This simulation frame work is also used to study the radiation reliability of NW CMOS devices and circuits. We undertake a detail study of the effects of variation of device design parameters to identify important design parameters, and their variability impact on the device performance. It is seen that device parasitics (series source drain resistance and capacitance), and the related device design parameters play a crucial role in determining device performance. We present analytical models to analyze the parasitic series resistance and capacitance, which are validated by simulations. These results are subsequently used in the analysis of the NW CMOS digital circuit performance. We note that the drive matching between n-, p-MOSFETs in NW/finFFET based CMOS circuits is a major issue due to current quantization arising from integral number of fins used. This results in mismatched noise margins and rise/fall delays in the NW CMOS circuits. Our study shows that, the dominance of the extension region in determining device performance can be used in tuning the drive current in NW based CMOS circuits. This approach, crucially, overcomes the current quantization issues in nanowire/FinFET devices. We present a novel approach using extension region as tuning parameter for drive current matching in Si-NW based CMOS digital logic circuits. It is noted that this approach is also applicable to FinFET based CMOS circuits. It is found that, the tuning of the device extension length or source/drain implantation dose provide significant enhancement in CMOS inverter and SRAM performance, when compared to conventional width (multi-NW) tuning approach. We further investigate Si-NW based SRAM cell performance with different drive tuning approaches: diameter, extension length, multi-NW and minimum area. We find that, when compared to multi-NW based tuning, the extension length tuning approach shows a significant improvement in power dissipation and active area consumption with nearly same noise margin and delay. Our results show that extension length tuned CMOS inverter and SRAM cell are excellent options for low power applications in NW CMOS circuits. Further, we investigate radiation response of the Si-NW CMOS devices and circuits. An analytical model for the impact of radiation induced silicon-oxide interface trap charge on NW device performance is developed, which is also validated by the simulation results. We see that a small (-40mV) change in the threshold voltage and subthreshold swing in the presence of large interface trap charge (lxl0'2cm 2). This demonstrates good radiation hard behaviour of the NW devices. These results are also corroborated by the experimental reports. The Si-NW CMOS inverter response to single event effects (SEE) is also analyzed using TCAD simulations. We see that NW CMOS is immune to SEE for linear energy transfer up to value of 0.1 pC/jim, which is much higher compared to planar CMOS behaviour. This can be attributed to small volume of NW devices. These results demonstrate good radiation immunity of NW CMOS and have high potential for application in high radiation environment.