Please use this identifier to cite or link to this item: http://localhost:8081/jspui/handle/123456789/17223
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dc.contributor.authorJoshi, Udaya-
dc.date.accessioned2025-06-26T12:59:40Z-
dc.date.available2025-06-26T12:59:40Z-
dc.date.issued2014-06-
dc.identifier.urihttp://localhost:8081/jspui/handle/123456789/17223-
dc.description.abstractA sliding DFT based frequency locked loop is proposed for global navigation satellite system receiver. Closed loop SDFT filter behavior is utilized to design the frequency locked loop. Magnitude phase spectra of SDFT filter operating in a feedback loop provide almost flat response around the center frequency. The small magnitude and phase error observed at the in-phase and quadrature component caused by frequency variation from center frequency can be adjusted by adaptive sampling frequency control. The incoming frequency of the receiver signal is estimated by correlating the quadrature component of SDFT and error obtained from the feedback loop. The sampling frequency - of SDFT is adjusted by numerically controlled oscillator with the help of estimated frequency. Hence large variation in input frequency could be estimated for bi-phase • signal of GNSS receiver. Simulation studies demonstrates the suitability of the FLL for GNSS receiver. Simulation results had been validated through the experimental investigation by implementing SDFT FLL using an FPGA.en_US
dc.description.sponsorshipINDIAN INSTITUTE OF TECHNOLOGY ROORKEEen_US
dc.language.isoenen_US
dc.publisherI I T ROORKEEen_US
dc.subjectClosed Loopen_US
dc.subjectMagnitude Phase Spectraen_US
dc.subjectSimulationen_US
dc.subjectQuadratureen_US
dc.titleDESIGN AND IMPLEMENTATION OF FREQUENCY LOCKED LOOP IN GLOBAL NAVIGATION SATELLITE SYSTEM RECEIVERSen_US
dc.typeOtheren_US
Appears in Collections:MASTERS' THESES (Electrical Engg)

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