DESIGN AND ANALYSIS OF JUNCTIONLESS FINFET AND ITS CIRCUIT/SRAM APPLICATIONS

Abstract

The down-scaling is still the most important and effective way for achieving the highperformance logic CMOS operation with low power, regardless of its concern br the technological difficulties, and thus. the past shrinking trend of the gate-length has been very aggressive. So too many problems i.e. short channel effects, compatibility issues and physical limits at lower dimensions arises. To overcome these problems introduction of new devices with improved electrostatic integrity is required. We propose a Lightly Doped Channel Junctionless Accumulation-Mode (LDC-JAM) FinFET that provides excellent electrostatic integrity as well as reduction in short channel effects (SCFs). It is observed that the drive current and the channel mobility enhance using proposed LDC-JAM FinFET. The effect of equivalent oxide thickness, fin thickness and source/drain doping concentration are also observed. The proposed LDC-JAM structure leads to better noise-margins with improved switching speed that is suitably demonstrated by a three-stage ring oscillator (R03). Moreover, the proposed LDC-JAM architecture also improves the performance of SRAM in terms of static-noise margins (SNMs) and access times. The hold and read SNM increases by 7.3% and 31%, respectively. Compared to the conventional junctionless (Conv-JLT) SRAMs. the LDC-JAM based SRAM demonstrates an improvement of' 28.7% and 12.34% in read and write access-times, respectively with a marginal trade-off in the write-margin. Design metrics comparison with respect to power supply scalability is also investigated over the Conv-JLT based SRAM. Further, we present the impact of spacer dielectric on junctionless transistor (JLT) FinFEl based circuit/SRAM memory cell. JLT FinFE'l's with spacers provide excellent electrostatic integrity as well as reduction in short channel effects (SCEs). Fringing electric field through spacer increases effective channel length in OFF-state whereas in ON-state it is unaf'fected. It is observed that the drive current, leakage current. drain induced barrier lowering (DIBI.) and sub-threshold swing (SS) are improved. The JLT structure with spacers leads to better noisemargins of CMOS inverter. Moreover. the JLT architecture also improves the performance of' SRAM in terms of static-noise margins (SNMs) and leakage power with increase in high-k - spacer value. I ligh-k spacer increase the capacitance of device, so ring oscillator delay and SRAM access times are degraded. - Further to improve the electrostatic integrity asymmetricity in the device is introduced. The iv effect of asymmetric source/drain doping on device characteristics are analyzed and a comparison between parameters of JAM and asymmetrically doped JLT is presented. Asymmetric doping in source/drain gives different characteristics for negative and positive supply. An improvement in leakage current, DIBL and SS is observed. Moreover, the proposed Asymmetric JLT architecture also improves the performance of SRAM in terms of static-noise margins and leakage power with degradation in access times. Design metrics comparison with respect to power supply scalability is also investigated over the Conv-JLT based SRAM.