PERFORMANCE ANALYSIS OF CARBON NANO TUBE BASED THROUGH SILICON VIAS

Abstract

During recent past, several researchers have designed the stacked IC layers on top of each other in order to integrate more devices on a single chip with improved performance. This advocated technique. known as 3D die stacking, primarily results in higher transistor density, improved speed. lower power dissipation and area. Traditionally, the connections were made through the multiple IP (intellectual property) cores on a single die (System-on-Chip), multiple dies in a single package (Multi-Chip Package) and multiple ICs on a printed circuit board (PCB). Later on, system-in-package (SiP) technology is introduced where dies containing ICs are stacked vertically on a substrate. Another stacking technique is package-on-package (PoP) that uses vertically stacked multiple packaged chips 4]. The latest development in this area is the 3D stacked IC using through silicon vias (TSVs) that employs a single package containing vertical stack of naked dies and allows the die to be vertically interconnected with another die. TSVs are primarily referred to as a vertical electrical connection "VIA" (vertical interconnect access) that passes completely through a silicon wafer or a die. Development of reliable 3D integrated system is largely dependent on the choice of filler materials used in through-silicon vias (TSVs). The conventional filler materials such as Cu, Al, W etc. have faced seveir electrimigration and fabrication related challenges. Therefore, researchers are forced to find an alternative solution for future high speed 3D based TSVs. Carbon nanotubes (CNTs) exhibit higher mechanical and thermal stability, higher conductivity and larger current carrying capability. This thesis presents CNT bundles as prospective filler material for TSVs and provides an analysis of signal integrity for different single- (SWCNT), double- (DWCNT) and multi-walled CNT (MWCNT) bundle based TSVs. An equivalent electrical model of coupled TSVs is employed to analyze the in-phase and out-phase delays. It is observed that using an MWCNT bundle (she1110), the overall in-phase delays are reduced by 96.86%, 92.33%, 78.35% and 32.72% compared to the bundled SWCNT, DWCNT, 4-shell MWCNT and 8-shell MWCNT, respectively: similarly. the overall reduction in out-phase delay is 85.89%, 73.38%, 45.92% and 12.56%, respectively. Additionally, a comparative analysis of power, delay and bandwidth is demonstrated for SWCNT and MWCNT bundle filled TSVs. A transfer function of d river- interconnect-load (DIL) system is obtained by representing the interconnect line with an equivalent single conductor (ESC) model of CNT bundle based TSVs. Using absolute frequency iv • response it is observed that the bandwidth of 10-shell MWCNT bundled TSV is larger in comparison to the SWCNT bundle. 4-shell MWCNT and 8-shell MWCNT bundle based vias. For high frequency applications silicon di-oxide (SiO2) cannot be used due to large fringing capacitance. 1-lence, polymer liners have provided potentially attractive solutions over conventional SiO2 in SWCNT bundle based TSVs. Using SiO2 and different polymer liners (such as benzocyclobutene. polypropylene carbonate and polyimide), this report analyzes the delay with and without crosstalk for different TSV heights and radius. It is observed that the crosstalk coupling is prominently influenced by the dielectric constant of the materials lying between the TSV and the Si substrate. For SWCNT bundled TSV with higher aspect ratio, the crosstalk delay is reduced by 38,9%, 30.7% and 12.3% for benzocyclobutene, polypropylene carbonate and polyimide, respectively, in comparison to conventional SiO2 liner.