MODELING AND DESIGN OF STT-MRAM

Abstract

The incredible potentials of Spin transfer torque (STT) Magnetic random access memories (MRAMs) give them an edge over other memory technologies. Most projections into the future show their gestation as universal memory technology; however, their evolution is still in a rudimentary stage. Attaining a high density in STT MRAMs is imperative to keep pace with the scaling scenario in FETs and hence commensurate them with future processors. With the intent of simulating the circuit before fabrication a suitable platform is needed; however, most simulation tools do not have the attributes for hybrid MTJ/FET design. Also one feels bereaved of SPICE compatible models for devices like vertical FET. This work addresses the above mentioned concerns and proposes a model for MTJ (coded in C++) and a simulation platform for hybrid MTJ/FET device-circuit co-design with physics based models. This model is validated using mixed mode simulations. Researchers are working ardently to use STTMRAMs for embedded applications, which have led to the rise of scaling challenges in STT MRAMs. In the conventional in-plane MTJ technology, the switching current is quite high (200-1200tA). Such high current drive could not be achieved with minimum sized transistors and hence scaling is not feasible for STT MRAM's with in-plane MTJs. However, the evolution of perpendicular magnetic anisotropy (PMA) MTJs (with switching current as low as 20-1001.tA or even less) can revolutionize the field of STT MRAMs. Consequently, one can see prospects towards increasing the integration density in STT MRAM's. With this objective in mind, Verilog-A model for PMA MTJ has been developed. Using this model, device simulation of STT MRAM with planar SOI FET has been performed and performance analysis of STT MRAM has been presented in this work. Further, recent advancement in the field of spin based electronics have led to the concept of novel architecture for computing wherein the logic and memory are merged together. The all spin logic (ASL) offers control, manipulation and storage of information without any requirement of external memory. Like MRAM, ASL also used magnetization state of nano-magnets for information storage. Design and simulation of such novel logic circuits has been a challenge due to lack of simulation tools that can promisingly capture spin transport and ferromagnetic properties. Over last couple of years graphene has been promisingly projected for spin based devices and logics. However, precise compact models to support efficient graphene based ASL circuit design do not exist. To fill this gap, a unified model based on lumped circuit approximation is presented in this paper for graphene based ASL and non-local spin valves.