STRESS EFFECTS ON SILICON NANO WIRE TRASISTOR

Abstract

The nanowire transistors have the best scaling potential, and hold high potential for future CMOS technology generations. Many experimental and modelling studies have demonstrated excellent performance of nanowire devices. In this thesis, we investigate GAA silicon nanowire FET using well calibrated Sentaurus TCAD process. The devices are implemented using CMOS compatible lateral nanowire process using top-down approach. The simulation framework is used to study the effects of stress on GAA junctionless silicon nanowire transistor. We present a novel approach, using gate oxide thickness and diameter of the nanowire as a parameter for varying stress and improving the device performance. It is found that using residual mechanical stress there is significant improvement in mobility in the channel region. These results demonstrates very good improvement in leakage current, subthreshold slope, and mobility