MODELING OF NEGATIVE BIAS TEMPERATURE INSTABILITY EFFECTS IN SILICON NANOWIRE TRANSISTORS

Abstract

Recent advances in semiconductor technology have led to need for novel device structures which overcome the drawbacks posed by traditional planar structures. One such non-planar alternative is Silicon Nanowire Field Effect Transistor (SNWFET) which offers better short channel immunity and improved transport properties. However, the reliability concerns for these devices have not been investigated thoroughly. Negative Bias Temperature Instability (NBTI) is one such reliability concern that affects P-type devices. It is observed as an unwanted increase in the threshold voltage, and a degradation of the ON state current. In addition, aging phenomenon and process variations add to the degradation in device performance. In this work we propose a model framework for NBTI effects in Silicon Nanowire Transistors, its comparisons with experimental results showing threshold voltage degradation, how it is dependent on various factors such as the oxide electric field, temperature and time, as well as the time exponents for different regions of the model explaining the saturation effect observed in Silicon Nanowire transistors. It was seen that the time slope for the Ni,vs time curve after saturation had a non-negligible value, which resulted in small increase in Vh beyond saturation. Also the fractional changes due to interface and oxide traps towards total V 1 shift were calculated and it was seen that the major degradation was due to interface traps with the oxide traps also contributing significantly.