NANOWIRE MOSFET MODELING AND CIRCUIT SIMULATION

Abstract

The surrounding gate MOSFET provides has better immunity against short channel effects, when it comes to below 32nm technology node. In order to analyze the performance of circuits based on vertical nanowire, a unified compact model of vertical nanowire is required. Accurate and fast compact models for transistors are one of the main pillars in circuit simulators. Indeed, compact models represent an interface between circuit designers and device technology. A compact model for circuit simulation of silicon based vertical nanowire is developed, which also include the effect of parasitic resistance and parasitic capacitance. The model is based on the solution of Poisson's equation and using which inversion charge is found. The model uses analytic expression for drain current, capacitances and terminal charges. The short channel effects threshold voltage roll-off, DIBL, velocity saturation and mobility degradation have been included. The model illustrates excellent match with numerical simulation of both the n-channel and p-channel 15 nm VNW nanowire. The model also takes care of the asymmetry at the device level due to the structure of VNW. At the - circuit level inverter is simulated and its transient and voltage transfer characteristics shows excellent matching with TCAD simulation. The model is then used for creating standard cell libraries of some of the basic gates at 15nm technology node. The timing and power parameters are measured using the H Spice simulation. Design flow of standard cell library is presented at I 5nm technology.