PARASITIC CAPACITANCE MODELING OF DUAL-K SPACER FINFET

Abstract

For the first time, an analytical model is developed for outer fringe capacitance of dual-k spacer DG FinFET. The model has been verified with simulation results for different parameters of the device like high-k spacer width, dielectric constant of high-k spacer and gate stack thickness. We observed that the model is in good agreement with device simulation result. The impact of gate underlap length and high-k spacer width on the parasitic capacitances of nanoscale dual-k spacer FinFET is studied in detail. The concept of underlap is used in non classical devices such as FinFET, to further improve the SCEs. It is observed that optimum gate underlap reduces parasitic capacitances at the expense of On-state drive current, because a potential barrier is generated near source side which restricts the carriers to flow from source to drain. To overcome this con of underlap devices, high-k spacer used, it improves on state drive current at the expense of large outer fringe capacitance. Outer fringe capacitance increases as high-k spacer width increases. So there is a trade-off between drive current and parasitic capacitances of the device. We have also analyzed the impact of gate electrode thickness on device performance by implementing a three- stage ring oscillator.