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http://localhost:8081/jspui/handle/123456789/16914Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Dutta, Ayan | - |
| dc.date.accessioned | 2025-06-20T13:39:08Z | - |
| dc.date.available | 2025-06-20T13:39:08Z | - |
| dc.date.issued | 2015-05 | - |
| dc.identifier.uri | http://localhost:8081/jspui/handle/123456789/16914 | - |
| dc.description.abstract | Downscaling of conventional MOSFETs in standard CMOS technology is becoming much tougher each day , since in nanoscale devices, quantum mechanics comes into effect & off-state leakage * increases drastically. In order to counter these obstacles , various transistor architectures like FinFET Silicon Nanowire FET etc have been invented. In this article , a novel idea for analytical modelling of Tn-Gate Silicon Nanowire FET structure has been proposed. This device is conceptualized to show ambipolarity & Dual-Threshold Voltage features , i.e. this uncommitted device can be operated as a pFET or nFET with high or low threshold voltage at the runtime , by electrically tuning its polarity gates | en_US |
| dc.description.sponsorship | INDIAN INSTITUTE OF TECHNOLOGY ROORKEE | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IIT ROORKEE | en_US |
| dc.subject | MOSFETs In Standard | en_US |
| dc.subject | CMOS Technology | en_US |
| dc.subject | Quantum Mechanics | en_US |
| dc.subject | Transistor Architectures | en_US |
| dc.title | ANALYTICAL MODELLING AND SIMULATION OF MULTI- GATE SILICON NANOWIRE FET FEATURING AMBIPOLARITY AND DUAL-THRESHOLD VOLTAGE CHARACTERISTICS | en_US |
| dc.type | Other | en_US |
| Appears in Collections: | MASTERS' THESES (E & C) | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| G25143.pdf | 3.84 MB | Adobe PDF | View/Open |
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