DERIVATION OF MECHANICAL STRESS AWARE STANDARD CELLS DELAY MODELS AND THEIR VALIDATION USING TEST STRUCTURES

Abstract

For the last few decades, CMOS transistors have been continuously scaled for achieving higher packing density and improvement in performance. 1-lowever, in deep submicron devices, expected performance is not obtained because of various short channel effects. In order to enhance CMOS performance below 90nm technology nodes, process induced mechanical stress is consistently used. Process induced mechanical stress improves the performance of CMOS circuits by enhancing the carrier mobility. Conventionally, Size of standard cell is increased by increasing the number of device fingers (NF) in layout as cell height is fixed. However, with increase in NF (which represents cell size) average value of stress in the channel alters considerably. This leads to a stress induced performance variability of standard cells as their size has changed and due to this their current carrying capability affects. Also, use of stressors makes CMOS performance dependent on layout. Existing delay models does not consider Layout dependent variability (LDE), thereby resulting into suboptimal designs. Therefore, it is desired that a model should be developed that considers LDE effects. This dissertation presents stress aware modified logical effort model for 2 input NAND gate. Additionally, a timing model two stage buffer is proposed which is further utilized in ECSM characterization.