MECHANICAL STRESS AWARE DESIGN AND LAYOUT OF BASIC ANALOG BUILDING BLOCKS

Abstract

As we know process induced mechanical stress is in an actual effect to improve performance of the transistor in sub-micron technologies. Carrier mobility improvement in transistor done by fortunate stress present in a channel using carrier redistribution and band deformation techniques [1]. Thus process brought up is layout reliant mechanical stress that's why the performance of the transistor is extremely sensitive based on layout parameters Due to stress induced LDEs, widespread study on what are the variations in performance of analog circuit. Firstly, due to stress induced LDEs, we have done the analysis of analog building block performance. In the second step, develop the models for LDE induced variations prediction. For developing prediction models, we are analyzing the performance variation based on changes done in the channel length after that developed subsequent models based on some other parameters. These models developed from the second step is helpful for the circuit designer in the circuit design phase of evaluation of performance margins and respective correction action performed. This analysis is useful for relative analysis for relative change of bias current with respect to changes made in channel length. For relative analysis, we used the single ended differential amplifiers, common source amplifiers and current mirrors of analog building blocks. At last, variation in channel stress due to change in channel length (L) is taken into account to design a common source amplifier. Differential Amplifier, Second Stage Operational Amplifier