IMPACT OF FINFET EXTENSION REGION PARASITIC ON ANALOG CIRCUIT PERFORMANCE

Abstract

Fin FETs are multi-gate transistors. The superior control of the channel by the gates reduces leakage currents, short channel effects and improve sub threshold slope. They are easy to fabricate and free of alignment problems that persist in other two gate transistors. The enhanced channel control made it possible to use wide fins at the same lOFF. But as two gate transistors are scaled down, output impedance (ro) reduces (due to high electric field at drain) whereas g1 is increased. The increase in gm is required as it result in an enhancement in cut-off frequency but the reduction in r0 drastically reduces intrinsic voltage gain , thus there is a trade-off b/w cutoff frequency and voltage gain .We discuss the impact of biasing points on FinFET's analog parameters and also explained reasons behind it. We also discuss source/drain extension (SDE) region design by varying spacer lengths to improve the analog parameters of FinFET's. Impact of FinFET extension region parasitic on analog circuit's voltage gain and cut-off frequency is also discussed.