GATE DIFFUSION INPUT (GDI) -A TECHNIQUE FOR LOW POWER DESIGN OF DIGITAL CIRCUITS

Abstract

As VLSI industry is being more demanding day by day in favor of Area, Power & delay of chips. Therefore requirement of innovation to decrease power, area, and delay is increasing because of fast development of portable applications like mobile, laptop, palmtop, notebook, cellular modem etc. That entire requirement became major concern which is more difficult for large digital combinational circuit designs. Traditional way to design logic circuits is CMOS technology in last two decades. After CMOS technology VLSI industry gives more innovations like Pass Transistor Logic (PTL), Complementary Pass Transistor Logic (CPL), Transmission Gate (TG), and Double Pass Transistor Logic (DPL). All these techniques gives improvement in Power, Speed & Area of digital circuits with some drawbacks of threshold degradation as it become major issue in VLSI industry due to small channel length of transistor. That cause gives need of more improvement in technology to complete the challenge of VLSI market. In this report we will discuss some new technologies to implement combinational digital circuits which will reduce more power, delay & area as compared to previous technologies. That is Gate Diffusion input (GDI) technology & further modification in GDI is Modified Gate Diffusion Input (M GDI) technology. Basically MGDI gives improvement in swing restoration problem of GDI technology also gives more reduced power, delay & area digital circuits. This technique is also maintaining lesser complexity of large digital circuits. Performance of GDI & M-GDI compared with traditional CMOS technology. This innovation is a boon for designing digital circuits, many large circuits can be implemented by two transistor only where as it takes 6 or more transistor to design by using traditional CMOS technology. That gives a large difference in prospective of area, propagation delay & area of circuitry. Whereas Power reduced from microwatt to nanowatt & delay reduced from microseconds to nanoseconds & picoseconds. Several logic functions & applications are implemented by GDI & M-GDI technology. Simulation of different logic functions has done by using cadence virtuoso in GPDK-45nm technology in terms of Power, Delay & Area improvement. Layout of these logic functions are also discussed in report. 4 Major application of digital combinational circuits Arithmetic Logic Unit (ALU) is simulated by using M-GDI technology compared with traditional CMOS technology & gives reduced power, delay & area.