A STUDY OF STRUCTURAL MODIFIED Si-TFET FOR ENHANCED PERFORMANCE

Abstract

The miniaturization of the devices and the innovation of the new structures in its fundamental limits provide a better way to improve the technological development of the semiconductor industry. As per day to day requirement of high speed and low power devices lot of research work is carried out on scaling to achieving the required goal. Most important elements in scaling are channel length, gate oxide thickness and for low power device supply voltage also consider as a scaling factor. The key device in the semiconductor industry is a MOSFET, which suffers from various issues due to its downscaling. The short channel effects and the power consumption of the MOSFET is a global issue and act as a driving force for the researcher to think about an alternative device structure. New devices with some geometric structure changes like SOI MOSFET, Double Gate FET, Tri-Gate FET, Fin FET, Surrounding Gate FET etc. are introduced. Tunnel Field Effect Transistor is one of the alternative devices with its promising behavior of abrupt sub-threshold slope and small leakage current and it has been proposed as an accompaniment for applications where low standby power dissipation is required. This dissertation focuses on the TFETs and its properties as well as the challenges in its operations is also taken into consideration. The ambipolar effects and the smaller ON currents are the major disputes of the TFET characteristics and to an obstacle, this limit different type of TFET structures are discussed. At the last, my dissertation work on the Double Source Tunnel FET (DS-TFET) has been discussed, which provides high drive current with smaller turn-on voltage for silicon based Tunnel FET. The superior tunneling area boosts the ION current for a smaller turn-on voltage. The arduous simulation study is performed in this for various performance parameters which have shown conspicuous improvement viz. Sub-threshold slope, ION/IOFF and so on