DESIGN OF CMOS CURRENT MODE LOGIC BUFFER CONSIDERING LAYOUT DEPENDENT EFFECTS

Abstract

CURRENT MODE LOGIC (CML) logic style is widely used in high frequency operations and data transfer. This logic style has significant advantages over its counterpart conventional CMOS Logic style because of its high speed, less delay and differential operation. However, it also has several shortcomings such as a static power dissipation and a large layout area etc. Therefore, CML logic style is primarily used for high speed data transfer and in high frequency operations. In this report basic CML Buffer has been investigated. The aim is to sufficiently reduce the propagation delay by utilizing optimum number of stages and device level phenomenon. We show that the delay of a buffer chain is highly dependent on number of stages and the tapering factor which is defined as the ratio of the size of the consecutive driving transistors. Primary focus of this work is to optimize the basic structure of the CML Buffer by using different structures for Resistive load and Current source. Later considering the layout dependent effects such as Inverse Narrow Width Effect (INWE) and process induced mechanical Stress, the layout of the buffer chain is optimized. It is observed that future goals in terms of area, propagation delay and power dissipation can be achieved using the above mentioned techniques in the basic buffer design.