DESIGN OF SUBTHRESHOLD SRAM FOR ULTRA LOW POWER APPLICATIONS

Abstract

SRAM occupies a major portion of SoC area. The performance of SRAM cells determines the performance of whole system. In SoC, power consumption is an important factor and it can be reduced effectively by scaling down supply voltage. This makes operation of SRAM cells in subthreshold region a viable choice for ultra-low power applications. High noise margins and low power dissipation are the major attributes of the SRAM cells used in ultra-low power applications. In this dissertation, a 10T Static Random-Access memory (SRAM) has been proposed with data aware dynamic feedback control and disturb free read. It enhances the write and read noise margins in the sub-threshold region. The dynamic threshold MOS transistors (DTMOS) technique reduces the power dissipation of the proposed memory cell. In this cell, single ended write operation is there such that the bitlines are kept at logic HIGH. It leads to large saving in dynamic power that occurs due to charging/discharging operation of bitlines. Therefore, proposed SRAM reduces the activity factor of discharging the bitlines for each write pattern. The proposed 10T SRAM cell has the wordline write margin (WVWL) of 2.47x and 1.59x as compared to iso-area 6T (iso-6T) and Schmitt Trigger based (ST2) SRAM cells respectively at supply voltage of 300 mV. Read access time (TRA) of proposed 10T is 0.52x and 0.89x of differential data aware 9T (DW9T) and differential 10T (D10T). Read operation in this cell is data controlled which helps in improving the read margin. Dynamic threshold technique increases read current for faster read operation. Read SNM is 2x, 1.16x and 1.4x of iso-6T, DW9T and ST2 respectively. The proposed cell does not suffer from contradicting read/write requirements as read and write operations are decoupled. These features enable the cell for ultralow power applications. The proposed 10T cell reduces the column half select issue but does not entirely eliminate it. In this dissertation as an improvement of this design, a 12T SRAM cell is also proposed. The proposed 12T SRAM cell makes the memory cell the half select free. It eliminates any possibility of undesired read and write operations in half selected cells in a row or column. A half-select free cell can be used for bit-interleaving hence proposed 12T SRAM cell is a viable option for bit-interleaving to combat half select issue. The proposed 12T cell is similar in working to 10T SRAM cell along with half select free feature with less than 10% overhead in area. The proposed 12T SRAM cell has 2.41x and 1.55x as compared to iso- 6T and ST2 SRAM cells respectively at supply voltage of 300 mV. Read access time (TRA) of proposed 12T is 0.53x and 0.9x of DW9T and D10T. Read SNM is 2x, 1.16x and 1.4x of iso-6T, DW9T and ST2 respectively. The proposed 12T provides almost equal margins as proposed 10T with half select free feature as trade-off for area penalty